https://newsroom.lamresearch.com/ https://newsroom.lamresearch.com/self-aligned-cfet-architecture-cmos-scaling Lam’s Semiverse Solutions team used digital twin modeling to explore a self-aligned CFET architecture that could help extend CMOS scaling beyond 10 Å. Tue, 29 Sep 2026 13:00:00 -0400 https://newsroom.lamresearch.com/self-aligned-cfet-architecture-cmos-scaling https://newsroom.lamresearch.com/silicon-valley-semiconductor-warehouse-built-for-velocity-resilience Lam Research’s new Silicon Valley warehouse speeds semiconductor parts retrieval and strengthens U.S. supply chain resilience. Tue, 29 Sep 2026 08:00:00 -0400 https://newsroom.lamresearch.com/silicon-valley-semiconductor-warehouse-built-for-velocity-resilience https://newsroom.lamresearch.com/panel-level-processing-advanced-semiconductor-packaging-semi-101 AI is increasing demand for larger and more complex chip packages. Traditional wafer-based packaging faces scaling challenges for large-format designs. Panel-level processing may improve... Tue, 08 Sep 2026 07:38:00 -0400 https://newsroom.lamresearch.com/panel-level-processing-advanced-semiconductor-packaging-semi-101 https://newsroom.lamresearch.com/lam-oregon-lab-expansion-accelerates-ai-chip-innovation Lam Research broke ground on a new advanced R&D lab in Tualatin, Oregon, expanding cleanroom capacity and strengthening its global lab network. Mon, 31 Aug 2026 13:21:00 -0400 https://newsroom.lamresearch.com/lam-oregon-lab-expansion-accelerates-ai-chip-innovation https://newsroom.lamresearch.com/virtual-fabrication-gaa-channel-non-uniformity Lam Semiverse® Solutions engineers used SEMulator3D® stress modeling to show how channel thickness, fin width, and lateral etch can be optimized to reduce stress non-uniformity and improve gate-all-around nanosheet transistor performance. Tue, 25 Aug 2026 17:37:00 -0400 https://newsroom.lamresearch.com/virtual-fabrication-gaa-channel-non-uniformity