- Stress differences can make one gate-all-around (GAA) channel carry too much current
- SEMulator3D® reveals these hidden imbalances before fabrication
- Channel thickness, fin width, and lateral etch all affect stress uniformity
Gate-all-around (GAA) nanosheet transistors are revolutionizing sub-5-nm CMOS chips, but a subtle design challenge has come into focus: the mechanical stress created in the nanosheet channels does not distribute uniformly across stacked GAA transistors.
Because stress reshapes the silicon band structure and directly changes carrier mobility,1 even small imbalances between the stacked nanosheets can distort device behavior in ways that are difficult to predict from geometry alone.
| What causes stress non-uniformity in GAA transistors? Stress non-uniformity occurs when stacked nanosheet channels experience different strain levels during fabrication. These differences affect carrier mobility, current flow, threshold voltage, and leakage. Using SEMulator3D® stress modeling, engineers can identify these variations early and optimize channel thickness, fin width, and lateral etch to improve performance. |
To illustrate, imagine that a GAA transistor’s stacked channels are three parallel highway lanes meant to carry traffic evenly. If one lane is smoother or wider than the others, more cars naturally shift into it. Similarly, if one nanosheet has higher stress and better carrier mobility, it could carry a disproportionate share of current, throwing off the device’s expected behavior.
Fixing this stress problem requires a tool that can emulate a sequence of semiconductor fabrication steps and proactively identify stress problems in the resulting three-dimensional structure.
Lam Semiverse® Solutions engineers used SEMulator3D® with integrated stress modeling to predict stress variations across GAA stacked nanosheets and learn how to improve stress uniformity. They identified how channel thickness, fin width, and lateral etch interact to drive non-uniform stress, revealing that a slightly thicker top channel dramatically improves uniformity.
Why Stress Uniformity Is Critical for GAA Nanosheet Transistor Performance
Figure 1. Gate-all-around field effect transistor architecture
A GAA architecture consists of isolated silicon channels stacked vertically between the source and drain. The channels are wrapped by the gate, which controls electron transport and the on/off state of the transistor. Stress or strain in the channels reshapes the silicon band structure and the carrier mobility, saturation current, off-state current, and threshold voltage.
Ideally, all GAA channels see identical stress and behave identically. In practice, process-induced variations cause them to see different stress or strain levels. The highest-stressed channel exhibits enhanced mobility and carries a disproportionate share of the current. A high-strain, low-Vt (threshold voltage) nanosheet channel can dominate off-state leakage, even if the other channels remain well controlled. This leakage current can create a spread in Vt and modify the effective turn-on characteristic of the transistor in unexpected ways. Uniform stress across the stack is therefore a critical design target, and simulation is essential because it is not obvious at the outset how to achieve it.
Using SEMulator3D to Simulate Stress in GAA Nanosheet Devices
We created a 3D process model of the GAA device by inputting layout, process step,2,3 and material information into SEMulator3D. We then explored predicted stress levels in the GAA channels using the generated 3D model with integrated stress analysis.
Stress is generated in the channels because of lattice mismatch between silicon and the epitaxially grown source and drain regions. For the pFET, the epitaxially grown source/drain material has a slightly greater lattice constant than silicon. The nFET source/drain material has a slightly smaller lattice constant than silicon.
During the replacement-metal-gate (RMG) process steps, the channels become freestanding, which allows these stressors to relax. The compressively stressed source/drain regions expand and push the pFET channels into compression, while the tensile stressed source/drain regions contract and pull the nFET channels into tension (see Figure 2).
Figure 2. Stress transfer to the silicon channel during the fabrication process
In the model, stress is solved during every major process step change: the epitaxial Si/SiGe stack, fin patterning, the gate module, source/drain growth, and the RMG module.
How Channel Thickness Influences Stress Uniformity in GAA Nanosheets
We executed a Design of Experiments (DOE) to test the impact of design changes on stress uniformity. The DOE varied the individual silicon layer thicknesses (Channel 1 to 3 thickness) and the fin width. Together, these parameters control the channel cross-section area, the primary driver of stress.
We extracted the average longitudinal stress (Sigma_yy) along a vertical cut of the channels (Figure 3). Three clear peaks of stress magnitude are shown, which correspond to the three nanosheets used in our model. These stress peaks are compressive for the pFET and tensile for the nFET. The three values are visibly different, with the nFET demonstrating larger stress non-uniformity or variability.
Figure 3. Control parameters for the DoE and the Sigma_yy along the z-cut of the channels for both pFET and nFET
Figure 4 represents stress non-uniformity (referred to as “stress difference”) using a contour plot as a function of the DOE variables. The stress difference for the pFET stays under 200 MPa, while the nFET stress difference reaches 400 to 800 MPa. The stress difference is most sensitive to the topmost channel’s (Channel 3) thickness. As Channel 3’s thickness increases, the stress difference decreases.
This is seen in Figure 4, as Channel 3’s thickness increases from 4 nm to 7 nm, and the red (highest stress difference) contours change to blue (lowest stress difference). This result indicates that the topmost channel (Channel 3) needs to be slightly thicker than the channels below to minimize the stress difference among channels.
Figure 4. Top channel thickness contributes most to stress non-uniformity
How Fin Width and Lateral Etch Affect GAA Stress Uniformity
The impact of fin width becomes pronounced when the fin lateral-etch ratio is high (Figure 5). The fin width is measured at the shallow trench isolation (STI) elevation for reference. The fin lateral etch ratio controls the fin taper and determines the channel width loss above the STI elevation.
Figure 5. The impact of fin lateral etch on the channel width
At a low lateral etch ratio, the fin taper is low, and channel width variation is not significant. At high lateral etch, the top channel becomes significantly narrower than the bottom. The interaction of fin width and fin lateral etch, for stress non-uniformity, is seen in Figure 6.
At a lower lateral etch ratio of 0.05 and 0.075, the stress difference contours do not change much as the fin width is reduced. At a higher lateral etch ratio of 0.1 (larger fin taper), the stress difference contours change as fin width changes. Specifically, for a narrow fin (25 to 26 nm) and thin channel 3 (4 to 5 nm), the stress difference in the nFET case is 900 MPa. If the fin width is fixed at 25 nm and Channel 3’s thickness is increased from 4 nm to 7 nm, the stress difference falls close to 500 MPa. The effect is weaker for the pFET but still present under an excessive lateral etch ratio.
Figure 6. Evolution of stress difference contours as a function of fin width and channel 3 thickness for different fin lateral etch ratios
Key Takeaways for GAA Nanosheet Stress Optimization
This study underscores the value of SEMulator3D beyond its use as a 3D process model builder or discrete process modelling tool. By emulating the full sequence of deposition, patterning, and gate-module steps and then solving for stress on the resulting 3D structure, it captures how subtle process choices impact device performance.
Spacer thickness, lateral etch, and individual channel thicknesses translate into mechanical variability across stacked nano-sheets. Coupling of complex semiconductor processing with high-fidelity stress simulation turns raw geometry into actionable design insight, allowing engineers to co-optimize channel thickness and fin width for uniform stress and predictable GAA device performance.
References
1 Thompson, S.E. et al. 2006. “Uniaxial-process-induced strained-Si: extending the CMOS roadmap,” IEEE Transactions on Electron Devices, 53(5), pp. 1010–1020.
2 Eneman, G. et al. 2020. “(Invited) Stress Simulations of Fins, Wires, and Nanosheets,” ECS Transactions, 98(5), pp. 253–265.
3 Rawat, A. et al. 2021. “Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks,” ESSDERC 2021, pp. 55–58.