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In this edition of Semi 101, we explore the evolution of transistor architectures that have enabled logic scaling.

In DRAM SAQP, small process variations can compound into pitch walk and, with LER, create line-bridge defects. Monte Carlo virtual fabrication reveals these interactions to tighten process windows and reduce wafer experimentation.

AI is compressing chip development timelines and raising the stakes for equipment suppliers Here is how Lam is responding Speed has always mattered in the semiconductor industry. What is different...

IBM and Lam Research have partnered in a five-year collaboration to develop processes that enable logic chip scaling beyond the 1nm node using high-NA EUV lithography.

The 2026 Lam Capital Venture Competition is a unique event that connects semiconductor startups with industry leaders, investors, and technical experts to advance AI-enabled semiconductor technologies.

SEMulator3D® Analytics is useful in calibrating FinFET device profiles, helping engineers achieve high precision in modeling fin etch depth and critical dimensions.

With AI's overwhelming demand for DRAM, Lam is accelerating its response with streamlined workflows and specialized tools help speed efficiency, yield, and cost savings.

Boise investment keeps Lam’s capabilities tightly coupled to customer roadmaps

DRAM scaling has reached the angstrom level—and the advanced architectures and processes that make higher performance and lower cost per bit possible. Watch now to see how memory keeps getting smaller.

Lam Research and CEA-Leti have formed a multi-year partnership to accelerate the development of specialty technology devices critical for AI hardware. This collaboration focuses on advancing materials, processes, and manufacturable solutions to improve energy efficiency and performance in AI data centers.