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AI is increasing demand for larger and more complex chip packages. Traditional wafer-based packaging faces scaling challenges for large-format designs. Panel-level processing may improve...

Lam Research broke ground on a new advanced R&D lab in Tualatin, Oregon, expanding cleanroom capacity and strengthening its global lab network.

Lam Semiverse® Solutions engineers used SEMulator3D® stress modeling to show how channel thickness, fin width, and lateral etch can be optimized to reduce stress non-uniformity and improve gate-all-around nanosheet transistor performance.

Lam's labs are part of a purpose-built, globally integrated R&D infrastructure designed to accelerate innovation across technology inflections.

Learn how feedforward control helps semiconductor manufacturers reduce wafer scrap and improve yield. Semiverse Solutions simulation demonstrated a pass-rate increase from 60.82% to 96.77% through intelligent process correction.

SABRE 3D is an electrochemical deposition solution engineered for precision copper plating (the critical wiring of modern semiconductor devices).

A joint paper from Lam Research, ASML, and imec puts 20 nm metal pitch in focus

AI is redefining semiconductor scaling Audrey Charles discusses the technologies, partnerships, and innovations that will define the future of semiconductor scaling AI is driving unprecedented...

A Lam scanning electron microscope technician shares how he started a career at Lam Research and continues his journey today as a lab supervisor.

SEMulator3D virtual fabrication optimizes backside power networks by modeling nTSV-to-BPR connectivity.