ALD Technology Fills Taller Memory
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Nov 30, 2020

Filling complex, high aspect ratio structures is a challenge for 3D NAND, DRAM, and logic chipmakers. Lam’s Aaron Fellis, vice president and general manager of dielectric atomic layer deposition (ALD) products, shared his thoughts with EE Times on how the Striker® FE enhanced ALD platform provides the performance needed to advance technology roadmaps.

Deposition technology plays a key role in advancing memory devices, and when it comes to 3D NAND, stacking exposes the limitations of current filling methods.

Lam Research’s recently announced Striker FE enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM. It employs advanced dielectric gapfill technology the company has dubbed “ICEFill” for filling 3D NAND and DRAM structures — as well as logic devices — in emerging nodes. The need for gapfill methods isn’t new, said Aaron Fellis, vice president and general manager of Dielectric ALD products, but the traditional ones no longer meet today’s needs, especially as 3D NAND is stacked higher. “They’re so tall and they have a number of different features that get etched through them to enable the integration of different steps,” he said. “Ultimately, they need to get filled back up with a dielectric material, most commonly silicon oxide.”

Legacy techniques, such as chemical vapor deposition, diffusion/furnace, and spin-on processes that are normally used as gapfill for semiconductor manufacturing are no longer viable for 3D NAND, Fellis said, due to trade-offs between quality, shrinkage, and gapfill voids. “They tend to shrink and distort the actual structure that the customer is building and designing.”

Continue reading at the EE Times website.