One-on-One with Lam CTO Rick Gottscho: Challenges in Stacking, Shrinking, and Inspecting Next-Gen Chips
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May 28, 2020

Lam Chief Technology Officer Rick Gottscho sat down with Semiconductor Engineering to share his insights on memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. Below, we share some excerpts from the article.

SE: EUV is finally happening. Now we have all of these node names. How do you see all this playing out? Do you see a mad rush to 3nm?

Gottscho: For sure, 3nm will be more difficult than 5nm, which was more difficult than 7nm. My understanding is demand is robust for 7nm and will be robust for 5nm. Some of the nodes are short-lived because they didn’t supply enough benefit, and our customers’ customers may be looking at the next node and hold off. It’s hard to determine which is going to be the killer node and which one may be short-lived. But the overall trend we see is continued demand for leading-edge devices. A lot of that is being driven by the big data activity in artificial intelligence, where you have to crunch an enormous amount of information and you don’t have forever to do it. High-speed processors, dense processors, and memory are critical.

SE: We have a lot of different memory technologies coming to market. What’s the impact of that?

Gottscho: It’s obvious that DRAM scaling is getting more and more difficult. We still see three more generations ahead, but the cost and performance benefits from each generation are getting smaller. Something has to fill the void. And then there is this storage-class memory space between NAND and DRAM, which PCRAM (phase-change memory) or XPoint memory fills partially, but not completely. PCRAM or XPoint can also create new end-use cases, thus opening up new vectors for market growth that didn’t exist with traditional NAND and DRAM. Our perspective is there won’t be one thing that replaces DRAM. We see a variety of solutions. There might be three or four variations that fill that space and replace DRAM or parts of the DRAM market. We believe that whatever the solution space consists of, it will involve 3D architectures.

SE: With 3D NAND, there is more bit density per node and more bits per cell. Is there enough demand for all of this?

Gottscho: There is strong demand long-term. There is explosive growth in data, and data generation and storage. All of these applications for mining the data are going to feed new applications for more data, so there is an insatiable demand for data and to store the data forever. There’s no reason why you can’t mine data you acquired 10 years ago and extract value from it, providing it is stored in a very accessible way. But if you think about 4-bit and 5-bit cells, Lam can make a difference here. You’re really digitizing a current/voltage characteristic. The precision with which you can divide up that I/V curve depends on whether this device looks exactly the same as the device right next to it or on top of it. So if your memory hole etch isn’t adequately uniform, then each device will be a little bit different in the array, and you’ll be doing a lot of error correction to make ‘this’ device look like ‘that’ device with 4 or 5 bits. The processing precision of both deposition and etch in building up 3D NAND structures is critically important, along with error correction and algorithms and circuitry to enable 5-bit cells.

SE: Where are we with ALE?

Gottscho: There are ALE solutions in volume production right now, and sometimes quasi-ALE. Just like ALD, you never really run at the limit because it’s too slow. So you make compromises and get close to that limit, and you get most of the benefits, and then you deal with the residual downside of not being at the limit. There’s a tradeoff between productivity and precision with both ALD and ALE. What we call mixed-mode pulsing is highly productive. There’s a spectrum of processes that get closer and closer to the ALE limit. That’s widely adopted. The big question is whether we can push this spectrum further toward a pure ALE or ALD process, because the benefits are significant. That applies to whether it’s an isotropic etch or an anisotropic etch. With gate all around, there’s an isotropic component that has to be done with extremely high selectivity. ALE would seem to be a natural process solution if you can make it sufficiently productive. That’s the challenge in ALE — how to make it faster.

Read the full article here: Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips