- A virtual DOE depends on the simulated device accurately matching its real-world counterpart
- SEMulator3D® Analytics allows engineers to calibrate models for accuracy down to > 1 nm
In modern semiconductor process integration, rapid and well-informed path finding is essential for on-time product release.
Virtual Design of Engineering (DOE) and predictive modeling can expose integration risks early; however, their value depends on accurate process models calibrated to real fab behavior.1 Reliable prediction requires strong correlations between model inputs and measurable outputs, enabling meaningful sensitivity analysis and optimization.2
SEMulator3D® Analytics accelerates this process through its “Identify Important Parameters” (IIP) and “Process Model Calibration” (PMC) features. These features can be used to rank critical variables and align models to experimental data.
Accurate calibration improves prediction fidelity, reducing fab experimentation cycles, cost, and time to market. In this article, we apply PMC to a FinFET device.
Calibration Targets
Calibration targets for a FinFET structure were extracted from transmission electron microscopy (TEM). Figure 1 displays a TEM-like cross-section of a FinFET silicon fin.
Figure 1. FinFET profile image similar to TEM cross-section images found in manufacturing.
Fin dimensions below the shallow trench isolation (STI) oxide were directly measured, while dimensions above the STI were inferred from the visible profile geometry. Measured and inferred values, listed in Table 1 (in nanometers), were used as calibration targets to align simulated profiles with actual experimental data. Measurement locations are shown in Figure 1.
Table 1. Critical dimension (CD), etch depth, and thickness
FinFET Modeling
The FinFET process manufacturing steps consist of:
- Self-aligned quadruple patterning (SAQP) to define the fin layout using a silicon mandrel, spacer deposition, and spacer etch.
- A fin cut step to remove fins from nondesigned regions.
- STI deposition and etch back process steps to expose the fins and reduce the upper fin width, producing a profile similar to Intel’s 10 nm SuperFin technology.3
Modeling Methodology
The process modeling platform software includes the following key modeling steps:
- SAQP-based model flow creation.
- Spacer deposition, spacer etch, and mandrel removal model steps to form the fin geometry.
- Fin etch modeling using a looping polymer deposition and silicon etch sequence with pattern loading effects.
- Fin etch and STI etch steps to reproduce the target profile.
- Virtual metrology to extract fin CD, silicon and oxide thickness, profile shape, and step height.
The polymer deposition factor settings produce a thickness difference between the inner (narrow) spaces and outer (wider) spaces. A thinner polymer passivation layer in the inner space results in increased silicon removal relative to the outer space. Pattern loading multiplier factors are applied at the start of the etch sequence for open (isolated) and dense array regions. These multipliers are combined with the corresponding values in the main etch step.
For this experiment, the etch ratio for the open mask is set to 1.0, while the etch ratio for the dense array is set to 0.75. This approach produces a differential polymer passivation thickness between the narrow and the wide spaces, resulting in increased silicon removal in inner spaces, as shown in Figure 2a. As the etch proceeds, the inner space slowly gets deeper than the outer space due to the difference in the polymer deposition thickness during the etch sequence. Final over etch depths were 120 nm (inner space) and 116 nm (outer space), as shown in Figure 2b.
Figure 2a. Etch polymer deposition difference between narrow and wide spaces. Figure 2b. Looping deposition and etch progression. The final etch depth is an inner space depth of 120 nm and an outer space depth of 116 nm, after the over etch step.
Profile Calibration
In this study, three challenging factors were incorporated into the virtual model:
- Etch polymer deposition was added to the model, along with multiple substrate etch selectivity ratios and loading effects. The target etch depth was achieved for each virtual run using a loop-until etch endpoint condition.
- Virtual metrology measurements were output from the device model to evaluate the success in matching the virtual and actual fin profiles.
- A final fin width adjustment was made prior to the gate deposition process step.
One thousand (1,000) simulation runs were performed in SEMulator3D using Monte Carlo simulation techniques under a uniform distribution. For each simulation event, virtual measurements were taken to quantify the simulation results. Thirty-three model variables were tested using the SEMulator3D Analytics “Identify Important Parameters” (IIP) analysis.
The analysis identified 10 key parameters that most impacted the profile calibration. Those key parameters were:
- Fin etch polymer deposition: Polymer thickness per loop and angular distribution of the deposition source particles.
- Fin etch: Etch depth per loop, lateral to vertical etch ratio of silicon and polymer, and etch angular distribution of the source particles.
- STI over etch: The lateral-to-vertical etch ratio and STI etch rate.
A virtual DOE for profile calibration was then executed using the SEMulator3D Analytics PMC package. Two thousand (2,000) Monte Carlo simulations were performed in SEMulator3D using a uniform distribution. Profile targets for critical dimension (CD) and etch depth were input. A strong correlation between the top (location A) and bottom (location E) fin CDs and the virtual model factors are seen in Figure 3.
Figure 3. Process response of top and bottom CD to two model factors: lateral to vertical etch ratio and angular distribution of the source particles.
SEMulator3D® Analytics PMC performed a linear regression calibration fitted to the previously run Monte Carlo virtual DOE experiment to optimize process model parameters. The goal of this step was to make the virtual 3D model match the actual physical device data, and to provide optimum settings for the simulation model variables. Ten calibration trials were started using random starting points. These trials converged to provide optimized parameter calibration values.
Table 2 displays calibration results for four of the 10 trials. The predicted virtual metrology measurements and the maximum deviation from the actual wafer-based target metrology values are shown in the table.
Table 2. SEMulator3D® Analytics calibration output
Figure 4. Run-4 optimum model computer-generated fin structure, post STI etch.
Results are very good, with the highest deviation from target ranging from 0.7 nm to 2.5 nm. Figure 4 displays the computer-generated fin structure post STI Etch, which had a maximum deviation from target of 0.7 nm (Run-4).
Conclusion
Fast, accurate pathfinding is essential for semiconductor process integration. Virtual DOE and predictive modeling help identify challenges early but require careful calibration. This study demonstrates FinFET model calibration using SEMulator3D Analytics, reducing 33 variables to 10 key factors and achieving sub-nanometer accuracy for fin etch depth and critical dimensions. This approach accelerates technology development and lowers experimental costs.
Brett Lowe is senior manager, Semiconductor Process & Integration Engineering, Lam Research Semiverse Solutions.
References
1 Pradeep Nanja “Building Predictive and Accurate 3D Process Models,” Semiconductor Engineering, September 21, 2020.
2 Hargrove et al. ”Review of Virtual Wafer Process Modeling and Metrology for Advanced Technology Development,” Journal of Micro/Nanopatterning, Materials, and Metrology, Vol. 22, Issue 3, 031209 (July 2023). https://doi.org/10.1117/1.JMM.22.3.031209.
3 TechInsights Staff. “Intel SRK02 Core™i7-1165G7 (Formerly Tiger Lake) 10 nm SuperFin FinFET Process Advanced CMOS Essentials,” TechInsights, 01/20/2021.