- SEMulator3D® software is useful for semiconductor process modeling and virtual design
- Engineers can easily and vividly visualize complicated 3D structures with the tool
Semiverse® Solutions, particularly SEMulator3D, can enhance semiconductor engineering in several ways. SEMulator3D is a software platform for semiconductor process modeling and virtual fabrication.1
- Prototyping and visualization: Virtual fabrication aids in understanding and visualizing complex semiconductor structures in three dimensions, facilitating better design and prototyping.
- Unit process development: The platform accelerates the optimization of semiconductor manufacturing settings, minimizing trial-and-error experimentation and reducing wafer usage.
- Process targeting and window enhancement: Virtual fabrication helps identify critical process specifications and windows, essential for developing advanced semiconductor technologies.
- Stress evolution at advanced nodes: Virtual fabrication can quantify stress-induced deformations in semiconductor structures, aiding in performance predictions without costly physical testing.
In this blog, we review some SEMulator3D virtual fabrication case studies published in recent years by our group. We also explore how virtual fabrication can reduce engineering workloads, lower research and development (R&D) costs, and decrease process development time.
Use Cases
1. Prototyping and visualization
Understanding and prototyping a device structure or process flow in three dimensions has become essential for semiconductor process development. Virtual fabrication can help with this task.
Figure 1 displays some complex 3D structures representing (a) advanced logic GAA (gate-all-around) logic devices with self-aligned backside contact, (b) 3D NAND memory using hybrid bonding, and (c) a 3D DRAM integration process sequence created using virtual fabrication.2
Virtual fabrication is a technique that can easily and vividly visualize these complicated structures and also model the processes used to build these structures.
Figure 1: (a) GAA, (b) 3D NAND and (c) 3D DRAM processes.
2. Unit process development
Finding the optimal semiconductor equipment settings to manufacture a semiconductor device when there is an exponentially large number of equipment settings available is a daunting task. This effort requires an increasingly large amount of trial-and-error silicon experimentation.
Virtual fabrication can accelerate this process and decrease wafer-based experimentation. A Design of Experiments (DOE1) was used to optimize a tungsten deposition-etch-deposition (DED) fill process in a bowed via (Figure 2). The purpose of the experiment was to design a manufacturing process that would lead to a void-free structure.
Two additional Design of Experiments (DOE2, a DEDED split experiment; and DOE3, an incoming bowing profile split experiment) were also undertaken. Using these types of virtual DOEs, the best process paths can be explored prior to performing wafer-based experimentation. Silicon wafer usage and process development time can be reduced using this virtual experimentation technique, accelerating time to solution.
Figure 2: Tungsten DED fill optimization DOEs to pursue a void-free structure.
3. Process targeting and window enhancement
The number of process steps required to build the latest semiconductor technologies has increased rapidly. Properly targeting process specifications and identifying process windows are vitally important tasks. Virtual fabrication can assist immensely with this work.
Figure 3 displays a virtual experiment where poly residue effects were virtually reproduced in a poly etch process to explore allowable process windows and device performance.3
Figure 3: Poly residue process window and device performance.
4. Stress evolution at advanced nodes
Our most recent study found that stress-induced deformation of GAA structures at advanced nodes can create potential performance and yield issues. Using virtual fabrication techniques, we investigated the impact of stress evolution and stress-induced deformation in a GAA structure during multiple process steps (Figure 4).
We were able to quantify the expected deformation using this technique without the time and cost of building and testing experimental devices.
Figure 4: Stress evolution and nanosheet bending in a GAA flow.
In each of these examples, we have demonstrated how virtual fabrication can improve semiconductor engineering at multiple stages of technology development. The capabilities of virtual fabrication and virtual twins during semiconductor development are limited only by imagination. It is time to embrace a seamless physical-virtual semiconductor ecosystem.
QingPeng Wang is a Semiverse Solutions senior semiconductor process and integration engineer.
References
1 Lam SEMulator3D page.
2 K. S. Choi et al. "A Three Dimensional DRAM (3D DRAM) Technology for the Next Decades." In Proc. IEEE Symposium. VLSI Technol. Circuits (VLSI), pp. 1-2, IEEE, 2024.
3 Q. Wang, D. Yu Chen, C. Li, R. Bao, J. Huang, and J. Ervin. "The Effects of Poly Corner Etch Residue on Advanced FinFET Device Performance." In Proc. China Semiconductor. Technol. Int. Conf. (CSTIC), pp. 1-3, IEEE, 2021.