- Using SEMulator3D®, ion beam etch (IBE) demonstrated improvements in EUV patterns
- Lam testing found the highest IBE angle of 80 degrees produced the best results
Driving the news: Extreme ultraviolet (EUV) lithography exposed resist patterns can exhibit excessive line edge roughness (LER) and line width roughness (LWR) due to random or shot noise.
Increasing the EUV exposure dose can reduce LER/LWR, but it also decreases wafer throughput, which is highly undesirable given the EUV tool’s high operating costs.
The Solution: Ion beam etching (IBE) can directionally etch away rough areas of the line and space resist pattern to improve LER/LWR. Using SEMulator3D®, we can simulate the result of IBE on resist patterns and determine the ideal etch conditions to improve LER/LWR.
IBE Basics
IBE accelerates a highly collimated beam of Argon ions (a beam consisting of parallel light rays, like a laser) toward a wafer. Etching occurs when there is an elastic collision of these ions with atoms on the surface of the wafer.
The ability to remove the atoms depends on the flux of the ion beam (number of ions striking a surface per unit time and area) and the surface normal (perpendicular directionality) of the ion’s travel path to the wafer material features.
Why it matters: By controlling the angle of the ion beam, we can selectively remove specific geometric features on the wafer surface. In the case of line and space patterns, LER and LWR can be improved using this technique.
IBE is a good way to improve the roughness of line and space patterns after EUV exposure, without having to increase the initial EUV exposure or decrease wafer throughput.
Testing Setup
Using the SEMulator3D® software platform, we prepared a line and space pattern with an initial LER of 1.64 and LWR of 2.31 (these are common values for EUV resists; see Figure 1). The line and space pattern has a half pitch of 26 nm and 54 nm, respectively. The total area to be etched was approximately 2 x 2 µm.
Figure 1: (Left) Line and space pattern with an LER and LWR consistent with EUV post-exposure. (Right) A height map profile of the resist line and space pattern.
To simulate ion beam etching, a visibility etch simulation with varying incident angles and etch depths was used. After this virtual etching, a height profile map was exported into an image, and the line edge roughness and line width roughness were measured using standard SEM image processing software. The incident angle was varied from 0 to 40 to 80 degrees, while the etch amount was varied from 0 to 20 to 40 nanometers.
LER and LWR at Varying Etch Angles
The first set of data (Figure 2) displays the LER and LWR for a 0-degree incident angle etch, or when the beam is collimated straight down.
When the sample is etched at 20, 40, and 60 nanometers, there was no improvement in the LER or LWR. This was expected since a vertical etch can’t selectively remove any protruding regions.
Figure 2: LER and LWR for a 0-degree incident angle etch
With a 40-degree tilt (incident etch) angle, we began to see improvement in the LER and LWR as the etch depth increased (Figure 3).
Figure 3: LER and LWR for a 40-degree incident angle etch
The best result, with the greatest reduction in LER and LWR, was obtained when the incident angle was set at the highest angle of 80 degrees (Figure 4).
Figure 4: LER and LWR for an 80-degree incident angle etch
Conclusion
In this study, we demonstrated that process simulation can replicate the effects of IBE to alleviate LER and LWR produced using EUV lithography. These simulation results are consistent with SEM images seen in IBE-etched samples. SEMulator3D can also be used to model more advanced IBE techniques, and more importantly, to help improve yield-limiting LER and LWR failures at advanced nodes.
Timothy Yang is a senior semiconductor process and integration engineer with Japan Semiverse® Solutions R&D. Connect with him on LinkedIn.