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• Stress analysis using virtual metrology and SEMulator3D assists in root-cause analysis  
• Engineers can address diverse and challenging issues during high-volume manufacturing  

With the semiconductor industry moving toward 3D DRAM, 3D logic architectures, and 1000+ layer 3D NAND stacks,¹ mechanical failures may become more common. Due to the complexity of these structures, mechanical stress from materials processing has the potential to significantly impact yield. 3D processing techniques (etching, deposition, and related chemistries), as well as material property development and optimization, will need to be adapted to meet the manufacturing requirements of these new 3D structures.  

But capturing the impact of mechanical stress during semiconductor process integration is a daunting task. Stress and strain in integrated structures are dependent upon the structure’s material properties and require special techniques to measure. Non-destructive measurement techniques are either low in resolution, or they require large and expensive extreme ultraviolet (EUV) or x-ray sources.  

To evaluate stress and mitigate its effects, predictive 3D process models can be used to predict the impact of mechanical stress on yield and performance. These models can capture the evolution of mechanical stress throughout a process integration flow and can be used to optimize material properties, establish optimal process windows, and reduce variability, while minimizing silicon-based build-and-test cycles.  

The Solution 

Semiverse™ Solutions offers a virtual fabrication platform (SEMulator3D®) that can be used to study process integration challenges and optimize and validate processes during high volume manufacturing. An integrated stress analysis module performs mechanical stress analysis during virtual fabrication, capturing how structural deformation evolves through the process flow.  

This stress analysis module seamlessly integrates stress analysis into SEMulator3D, providing automated virtual metrology to assist in root-cause analysis. Within the integrated environment, both process and design can be optimized to alleviate the impact of mechanical stress throughout a process flow, reducing the number of design cycles and accelerating yield ramp. 

Analyzing Stress in GAA FET Manufacturing 

Figure 1 displays an example of stress/strain evolution during process integration of a GAA FET device. During manufacturing, the GAA FET device topology changes with each process step. SEMulator3D stress analysis can display how stress and strain evolve step-by-step during virtual manufacturing steps. This provides a comprehensive picture of stress history and enables the study of “memorization” effects.  

More importantly, root-cause-analysis of stress issues can be performed by backtracking specific sources of stress, and modifications of material properties or integration choices can be tested to better understand the consequences of these choices on stress and/or deformation in the device.  

Figure 1:  Stress/strain evolution during process integration of a GAA FET device 

This is just one example of how virtual fabrication can be used to identify and mitigate stress-based structural failures that impact yield, by backtracking stress results throughout the relevant series of process steps. The same technique can be applied across the manufacturing process for different types of semiconductor chips: 

• Logic during critical front end of line (FEOL) stages  
• 3D NAND during staircase formation, slit etching, word line, and slit fill processing 
• DRAM process flows from the active area through the capacitor process module 

Using virtual fabrication in SEMulator3D, the progression of mechanical deformation or stress deformation evolution can be visualized on 3D silicon-accurate device structures. Mechanical stress due to intrinsic stress, thermal expansion, and crystal lattice mismatch can be virtually introduced throughout the material in a 3D structure. Combined with process and design data, mechanical stress and deformation can be evaluated across the entire process flow. 

Value of Integrated Stress Analysis 

SEMulator3D can execute detailed process integration flows and generate true to silicon, realistic 3D structures. The platform also allows the execution of large, automated Design-of-Experiments to test the impact of process changes on device performance. Automated modeling of stress evolution and deformation during all process steps is supported, along with global virtual metrology and powerful ML/AI to identify root-causes and potential mitigation.  

These capabilities provide semiconductor engineers with the ability to address diverse and challenging stress issues during semiconductor development and high-volume manufacturing. Typical use cases include: 

• Stress backtracking for source identification and mitigation 
• Technology stack optimization for films with tunable stress and low thermal shrinkage 
• Monitoring of stress accumulation and release during patterning stack – stress distribution and optimization 
• Guiding design and structural assumptions toward robust, low-stress process, materials, and integration schemes 
• Identifying and providing an early warning to engineers about structural failures due to stress 
• Progressive effect analysis of stress induced deformation 
• DTCO for patterning and for preventing wiggling due to spacer deposition 

Ivan Chakarov is director of product management at Lam Research Semiverse™ Solutions. 

¹ Harmeet Singh, The Path to 1,000 Layers Will Be Etched, Lam Research, https://newsroom.lamresearch.com/1000-layers-NAND-etch 

Caution Regarding Forward-Looking Statements

Statements made in this article that are not of historical fact are forward-looking statements and are subject to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Such forward-looking statements relate to but are not limited to: market and industry trends; the potential benefits of and applications resulting from virtual fabrication and our mechanical stress solutions. Some factors that may affect these forward-looking statements include: trade regulations, export controls, trade disputes, and other geopolitical tensions may inhibit our ability to sell our products; business, political and/or regulatory conditions in the consumer electronics industry, the semiconductor industry and the overall economy may deteriorate or change; the actions of our customers and competitors may be inconsistent with our expectations; supply chain cost increases and other inflationary pressures have impacted and may continue to impact our profitability; supply chain disruptions or manufacturing capacity constraints may limit our ability to manufacture and sell our products; and natural and human-caused disasters, disease outbreaks, war, terrorism, political or governmental unrest or instability, or other events beyond our control may impact our operations in affected areas; as well as the other risks and uncertainties that are described in the documents filed or furnished by us with the Securities and Exchange Commission, including specifically the Risk Factors described in our annual report on Form 10-K for the fiscal year ended June 30, 2024 and our quarterly report on Form 10-Q for the quarter ended December 29, 2024. These uncertainties and changes could materially affect the forward-looking statements and cause actual results to vary from expectations in a material way. The Company undertakes no obligation to update the information or statements made in this article.