- Future logic devices depend on advanced patterning to scale < 1 angstrom
- Chips having more functionality in a smaller area are made with advanced patterning
The next generation of semiconductor devices hinges on building the most advanced semiconductor chips with the smallest features the industry has ever produced. Manufacturing these incredibly small features in logic, DRAM, and NAND devices will require advanced patterning techniques.
Advanced patterning is critical for upcoming tech inflections
Advanced patterning involves sophisticated deposition, etch, and lithography tools and techniques to create extremely small and precise features in advanced semiconductor devices—often just a few atoms wide. These techniques allow manufacturers to fit more transistors onto a single chip and increase overall performance and functionality both in memory and logic devices.
In addition to increasing overall performance, the use of advanced patterning techniques, compared to traditional patterning methods, creates larger process windows that help provide higher yields, fewer defects, and improved cost efficiency in smaller dimensions.
Understanding Techniques
One of the key steps in creating patterns, which eventually become circuits, on a wafer is exposure by a lithography scanner. An exposure refers to the process within a scanner in which light is transmitted or reflected onto a photomask that holds the pattern of one layer of a chip. After being patterned, the light is then projected onto the scanner’s mirrors, reducing it by a factor of 4x until it reaches the wafer coated with a light-sensitive material called photoresist.
- Companies like ASML, Nikon, and Canon make exposure tools, more commonly known as steppers and scanners, where scanners are the most recent and technologically advanced.
- ASML is the sole producer of the most advanced scanner in the industry, using EUV (extreme ultraviolet) technology (discussed below).
Lam Research supports the extreme ultraviolet (EUV) process with our innovative Aether® dry photoresist deposition and development process used before and after EUV exposure.
Single Patterning
The single patterning method uses a single exposure step to create the desired pattern of one layer of a chip. Semiconductor manufacturers often prefer single patterning because it is the simplest and most cost-effective method, as long as the lithography process has the capability to achieve the resolution required for the chip pattern’s smallest features.
As chip sizes shrink and transistor density increases, the choice is either to switch to a more capable scanner and process or to employ a multi-patterning strategy. Below are some of the multi-patterning techniques used today.
Multi-Patterning
As the need for smaller features and denser patterns outpaces developments in advanced exposure tools, multi-patterning techniques come into play. This approach uses multiple photomasks and exposures in an additive way to create precise and compact patterns that outperform the resolution limits of a single lithography exposure.
Although managing multiple exposures can complicate pattern fidelity and potentially reduce placement accuracy, these techniques are essential for producing the complex layouts demanded by modern chip designs.
Double Patterning Technology (DPT): This is a straightforward form of multi-patterning. It involves breaking the pattern into two separate exposures (i.e., two separate photomasks), enabling the printing of small and densely packed features.
- Litho-Etch-Litho-Etch (LELE): This DPT technique involves patterning one photomask, (using exposure and etching). Then the complementary photomask is patterned with a new coating of photoresist and etched again, with patterns printed in the spaces left among the features of the first pattern.
- Litho-Freeze-Litho-Etch (LFLE): This DPT technique involves exposing the first photomask, performing a treatment step to retain (freeze) the pattern onto the photoresist before exposing the second complementary photomask. The double-patterned photoresist, when processed, retains and produces the complete pattern.
Triple or Quadruple Patterning Technology (TPT, QPT): When double patterning is not enough, the patterning process can be broken out and repeated in three or four steps using three or four photomasks to create even finer and denser patterns.
Self-Aligned Patterning
Self-aligned patterning involves using sidewall spacers or other methods to form small features without relying on conventional lithography alone.
Self-Aligned Double Patterning (SADP): In SADP, a mask is patterned using lithography, and then sidewalls (called spacers) are formed around the patterned features. The spacers then serve as hard mask patterns for etching smaller features instead of the patterned photoresist features themselves. A second patterning step is then performed to trim spacer ends or to cut spacers into smaller pieces since a single exposure may not provide sufficient resolution.
Self-Aligned Quadruple Patterning (SAQP): This process uses two cycles of the SADP process described above to achieve even smaller and denser features.
Self-Aligned Litho-Etch-Litho-Etch (SALELE): This technique involves a specific form of double patterning where a layer is patterned and etched, and then another layer is deposited and trimmed using the features of the first pattern as references.
EUV Lithography
Advanced patterning employs state-of-the-art methods, such as extreme ultraviolet (EUV) lithography, to produce features in the sub-10-nm range.
EUV lithography is a type of photolithography that uses the smallest lithography wavelength available (13.56 nm) to create the most intricate patterns on a wafer. It’s called “extreme ultraviolet” because it is at the extreme edge of the UV portion of the electromagnetic spectrum.
Over the years, EUV photomask making has continually improved to meet stringent requirements at the 7-nm and 5-nm nodes, making EUV lithography increasingly reliable for high-volume production. However, developing equipment and process for photoresists that can better handle high-energy EUV light while maintaining precision is a continuous effort. Lam’s Aether dry photoresist process technology provides one such solution.
Patterning Challenges
A key challenge to overcome in patterning techniques is edge placement error, or EPE. Stochastic (random) defects in photoresist films and nonuniform EUV exposures caused by a vastly reduced number of available photons, combined with across-wafer feature size and position nonuniformities due to scanner errors, all add to the total EPE.
- These errors are manifested as critical dimension (CD) errors, bridged and broken lines, missing (closed), “kissing” (bridged) holes (contacts), or misplaced feature edges in the same layer and/or with respect to preceding and subsequent layers (e.g., overlay error), etc.
- EPE is measured according to the type of error (CD size, bridge/break, overlay, etc.). The margin of error for EPE is already impossibly small at 5 nm, which means chipmakers need all features to line up across the entire wafer within 5 nm by simultaneously minimizing all EPE sources. By 2040, that margin will be reduced to 3 nm, which means a margin of just a couple dozen atoms!
Some devices have a defect tolerance of less than one defect per wafer, which is an incredibly small tolerance when considering that a wafer can comprise hundreds of billions of transistors.
- A defect is a short or an open circuit, which prevents the chip from functioning and therefore reduces overall yield in high volume manufacturing.
Using advanced patterning to increase the density of device structures, while extremely difficult, leads to several benefits beyond just performance and functionality. It promotes cost efficiency by enabling the production of more chips per wafer, and it contributes to energy efficiency through the creation of chips that consume less power.
Until recently, cost efficiency was the industry’s main goal. Now, doing all this while improving sustainability has become a high priority for chip manufacturers, as well as for equipment and material suppliers.
Lam’s Solutions
Traditional patterning methods can no longer meet the resolution requirements as the semiconductor industry moves toward smaller nodes like 5 nm, 3 nm, and beyond. Advanced techniques are crucial for meeting the demands for high-performance, low-power, and highly integrated semiconductor devices that will continue to push the pace of innovation in the industry.
Lam has a suite of patterning solutions that enable logic and DRAM scaling at a lower cost by extending single print EUV lithography to more advanced nodes. This suite of dry patterning solutions allows us to make those impossibly small features and put them in the right places.
- Lam’s Akara®: Provides extreme precision and repeatability, best-in-class pattern fidelity, and high yield by minimizing defects on the wafer. Akara is the fastest etcher available and can pulse plasma in ways that were not previously feasible or practical. It is designed for improved sustainability and efficiency to drive lower TCO.
- Lam’s VECTOR® DT: Uses dry deposition to put a very strong stabilizing film on the back of the wafer to keep it as flat as possible, resulting in improved overlay of 20-25%.
- Lam’s Corvus®: Provides edge control technology that supports overlay by ensuring ions are directly perpendicular to the wafer's surface.
- Lam’s Kyber®: Incorporates advanced Ion Beam treatment to reduce line edge roughness (LER) by 60% at a significantly lower cost than EUV.
- Lam’s Aether®: This dry EUV photoresist deposition and development processing technology is a revolutionary way to achieve the highest yield on the most demanding lithography specifications while reducing the overall cost of EUV patterning.
Glossary
Nonuniformities – Variation or inconsistencies in the material properties, dimensions, or performance across a wafer or device.
Pattern fidelity – The accuracy with which the patterns created during the lithography process match the intended design.
Photomask – A stencil or template used in the photolithography process that contains the desired circuit pattern and blocks light in certain areas.
Photoresist – A light sensitive material applied to the surface of a wafer. When exposed to light, it undergoes a chemical change that allows specific areas to be developed and others to be washed away.
Photoresist baking - Heating steps applied to the photoresist material after it has been applied to the substrate.
Process window – The range of conditions under which a specific manufacturing process can be effectively carried out to achieve the desired outcomes.
Resolution – The smallest feature size that can be reliably created or resolved during the lithography process.
Stochastic defects – Random unpredictable variations that occur during the fabrication process.
Transistor – Fundamental component in semiconductor devices used to amplify or switch electrical signals and electrical power.
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