- Pattern-dependent etch can lead to variations across the same chip
- Dummy fill and SEMulator3D® help reduce shallow trench isolation and recess nonuniformity
As semiconductor patterning continues to scale, even small layout nonuniformities can lead to noticeably different process outcomes. Real chip layouts contain a mix of dense regions, large open regions, and isolated features. As a result, the etch process encounters different “local environments” across the wafer. Even with the same process settings (or recipe), some areas may etch more than others, creating pattern-dependent variation.
What Is Pattern-Dependent Etch Variation?
Pattern-dependent variation means the same manufacturing step can produce different results, depending on what the nearby shapes look like.
In this article, I use the examples of Shallow Trench Isolation (STI; a set of etched trenches that separate neighboring transistors so they don’t electrically interfere) and recess (when the etched depth becomes deeper than intended or varies by location) to illustrate how pattern-dependent variation occurs.
Causes of Pattern-Dependent Variation
During the trench etch step of STI, the depth (recess) can vary depending on where the trench is located on the chip. If STI nonuniformity increases, it can be amplified in later steps (such as film deposition, planarization, or subsequent etch/clean steps), ultimately reducing the process margin that supports manufacturing success. If the trench is too deep in some areas, later layers won’t sit flat, which can affect device performance. In other words, STI recess uniformity is not just a “single-step issue”—it can become a starting point that impacts downstream process quality.
So why can STI recess differ even under the same recipe? The main reason is usually the difference in the surrounding layout environment. Dense and open regions can differ in:
- how reactants are supplied,
- how byproducts are removed, and
- how plasma/ion conditions effectively reach the feature.
Loading Effects
As these differences accumulate, a loading effect can appear, where areas with more material to etch can “use up” reactive species faster, so etch rate and profile vary by region.
Aspect Ratio Dependent Etching (ARDE)
In addition, as features become narrower and deeper, reactant transport becomes more difficult, and etch behavior changes due to Aspect Ratio Dependent Etching (ARDE). ARDE occurs when deep, narrow features etch more slowly or differently because it’s harder for etching chemicals and byproducts to move in and out.
Together, loading effect and ARDE can increase local STI recess variation.
In short, the process problem looks like this:
How Dummy Fill Improves Etch Uniformity
One practical way to reduce this variation is to perform dummy fill processing. Dummy fill steps add nonfunctional shapes to the layout to reduce pattern density differences. This helps the process “see” a more uniform environment across the layout, which can reduce pattern‑dependent variation such as recess nonuniformity.
However, dummy fill is not a universal fix. Its impact can depend on where it is placed, how much is added, and what shapes are used. A practical challenge is quickly determining which dummy fill options are most effective. Verifying layout changes in silicon often requires reticle (the photomask used to print the chip pattern) updates, which adds time and cost.
That is why simulation can be helpful. By comparing the results before dummy fill operations are used (the baseline process of record) versus after dummy fill inclusion (under the same process conditions), we can estimate how the dummy fill step can impact recess metrics such as the mean, range, and standard deviation.
This approach is not about reproducing a specific reference as a single correct answer. Instead, it focuses on quickly understanding the comparisons and tradeoffs needed for decision‑making.
Simulation Study Using SEMulator3D®
To quickly evaluate the addition of dummy fill steps to our manufacturing process, I used 3D process simulation in SEMulator3D® to compare a baseline layout (the POR) and peripheral dummy-fill layouts under the same process conditions.
Because real circuit layouts inherently include irregular patterns, this study uses part of a representative SRAM (static random-access memory) circuit layout exhibiting asymmetry as the POR (Figure 1). SRAM layouts are a common, realistic example with lots of repeating and nonrepeating features, making them useful for stress-testing uniformity.
Figure 1. POR (SRAM) layout
Results: Dummy Open Density vs. Recess Variation
I wanted to see whether trench depth varies even when the linewidth is the same. First, I examined the critical dimension (CD)-to-recess relationship, using the POR manufacturing conditions without including the dummy fill processes. I selected nine random locations across different layout neighborhoods and compared the STI recess values at those locations (Figure 2a). Using this layout resulted in a structure with irregular spacing, as shown in Figure 2b.
Figure 2a. Measurement locations for POR device model. Figure 2b. 3D structure from POR device model
I found that even locations with the same CD could show a much larger recess range (Figure 3).
Figure 3. STI recess value (in nanometers) versus STI CD at nine measurement locations
Since the goal here is not the CD trend itself but rather achieving a more uniform recess regardless of CD, I focused on recess variation.
POR Summary
The recess standard deviation of 8.2 nm was calculated using results from nine measurement points. The key point here isn’t whether the absolute numbers are “good” or “bad,” but how much the spread shrinks after applying dummy fill.
Five Shape Options
To improve the recess standard deviation, I prepared five dummy fill options to modify the POR device geometry:
- DP1: dot pattern
- DP2: horizontal bar
- DP3: vertical bar
- DP4: angled pattern
- DP5: no‑fill in the dummy window
I used a measure called “dummy open density” to compare the effectiveness of different dummy pattens in reducing (or improving) the recess standard deviation (Figure 4). Dummy open density is a measure of the device pattern density, or what percentage of the dummy patterning area has been removed. For example, if a 100×100 area has 30% etched away as openings, the open density is 30%.
When comparing dummy open density and recess standard deviation, this study indicated that a higher open density corresponds to improved recess standard deviation (Figure 4).
Figure 4. Dummy open density versus STI recess standard deviation
Discussion
One possible explanation of the results is that increasing the open density reduced the effective layout contrast seen during the etch process, which weakened pattern-dependent effects in the model. In other words, with more dummy features added, dense and open regions looked more similar to the etch process, so the etch behaved more consistently from place to place.
Note: This finding should not be taken as a universal rule that higher open density is always better. Instead, it suggests that for this layout and process settings, peripheral dummy fill (etching) may have reduced local environment differences and weakened loading/ARDE effects. Additional checks with other layouts and process windows would be needed before applying the idea broadly.
Simulation as a Fast Feedback Loop
As scaling continues, layout–process interactions become increasingly important. Dummy fill can be an effective lever to reduce variation driven by differences in the patterning environment. Fast simulation-based feedback can help prioritize dummy layout strategies and other process options outside of the fab leading to improved yield and time to market.
HJ Kim is a semiconductor process and integration engineer with Lam Korea Semiverse Solutions R&D.
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