With all the attention being given to AI, it’s easy to overlook some of the core technologies enabling its capabilities. Sure, a lot more people have now heard about NPUs, GPUs and the businesses that make them, but what about the companies who enable these cutting-edge AI accelerators to be manufactured?
The Complexity of Modern Chipmaking
While most people don’t realize it, chip manufacturing is incredibly hard and requires the level of scientific breakthroughs that have powered humanity’s most advanced achievements. I mean, we’re talking about bending the laws of physics in order to build components that are a thousand times smaller than a grain of sand. Oh, and doing so millions of times over at incredibly high levels of quality and consistency. Plus, with the extra demands that GenAI workloads are putting on today’s latest chips, the challenges are getting even tougher.
That’s why companies providing the equipment and technologies that enable the manufacturing of these advanced chips play an essential role in driving the advanced AI capabilities we are all starting to experience.
Without their work to overcome technical challenges like the need for exascale computing, addressing the “memory wall” that can slow down AI accelerators, increasing power efficiency and other issues that are necessary to maintain the Moore’s Law-like advances we’ve seen in these chips, the state of AI would not be where it is today. In particular, organizations like Lam Research, who build extremely complex, sophisticated machines that help process the raw silicon wafers that eventually become today’s most powerful semiconductor chips, play a big, though little understood part in big tech advancements like AI.
Building Next-Generation AI Chips Through Heterogeneous Integration
Lam Research makes a wide array of equipment that performs multiple tasks in the highly precise, extremely complex and long (often 30 days or more) process of creating a modern chip. But in the era of AI accelerators, it turns out even the most sophisticated individual chip isn’t enough.
Instead, the latest GPUs and other advanced processors are being put together through a process called heterogeneous integration that takes multiple independent elements called “chiplets” and packages them together into even more sophisticated pseudo-SOCs or Systems on Chip (advanced multi-chip packages that mimic some characteristics of an SOC). Commonly referred to as advanced packaging, the technology that enables the creation of these psuedo-SOCs requires extremely sophisticated semiconductor manufacturing.
Extraordinarily precise component stacking, chip-to-chip connections, and other key technologies allow these chips to integrate multiple independent processing elements, separate connectivity elements, memory, and more. The ultimate goal is to create the most powerful and capable multi-chip package they can in the most effective and efficient space and power envelopes possible.
Advanced Packaging Techniques
As with individual wafer processing, there are often multiple steps and multiple technologies (and approaches) involved with chip packaging. Some entail direct side-by-side connections between various chiplets and other elements, while others use various forms of stacking technology where different pieces sit on top of one another. In all cases, a critical part of the packaging process involves creating the paths through which the connections between the various elements are made. Sometimes those paths are created through film layers that act as a type of “glue” between the elements while in other situations it may involve creating millions of tiny holes that are filled with a metal-like material that provides something akin to a physical bridge between the layers.
In the case of Lam Research, the company has developed machines for each of those core packaging technologies. For physical bridging types—which are called through silicon vias or TSVs—Lam offers products in their Syndion®, Striker® ALD and SABRE® 3D lines. Each performs different parts of the process, including etching for creating the holes, deposition and filling for both lining and then injecting the new material into the holes, and then various cleaning processes along the way.
Lam's VECTOR® TEOS 3D Enhances Reliability in Advanced Packaging
One of the company’s most recent developments involves a technology called die-to-wafer hybrid bonding, which is used to essentially glue various stacked elements together. The new Lam Research VECTOR® TEOS 3D machine is technically referred to as a dielectric gapfill tool. It applies a layer of material that serves as both a buffer and connector between stacked chiplets. (Specifically, they’re engineered dielectric layers that provide electrical isolation and mechanical stability.)
One of its key attributes is the ability to apply what, in the world of semiconductor manufacturing, is considered a thick layer of the material that starts at 20 microns and can scale to over 100 microns. (For perspective, many other thin film deposition tools used in chipmaking measure their thickness in submicron to individual microns.)
The thickness of the film is considered critical for reliability in the extremely precise world of semiconductor manufacturing because it ensures that no gaps will exist between the stacked layers and that, in turn, means that fully functional chips can be produced on a more consistent basis.
In addition to the film thickness, VECTOR TEOS 3D also has the ability to essentially flatten wafers that may have started to bow in the manufacturing process. It turns out that because of how chip stacking works, the potential for this bowing problem is much greater than it might be with individual, non-stacked chips.
As a result, in order to maintain the extraordinarily tight tolerances and precision required for advanced chipmaking, this de-bowing process is a critical capability to maintain the high yields that modern chipmakers need.
One last benefit of the VECTOR TEOS 3D is much easier to understand: it uses a quad chamber design, allowing it to process four wafers at the same time, which boosts throughput.
Semiconductor Manufacturing Innovations Enable AI Progress
Though little understood, the advancements in AI acceleration that have been achieved to date are strongly tied back to the manufacturing technologies that enabled them to be built. Integrating things like High Bandwidth Memory (HBM) directly beside GPU cores, for example, has had a huge impact on the performance, scale and efficiency of the latest AI accelerators and that, in turn, is driving the impressive advancements we’ve seen in Large Language Models (LLMs) and other AI applications.
Looking forward, it’s going to be continued advancements in 3D packaging—along the lines of what Lam Research is doing with their new VECTOR TEOS 3D tool—that allow those advancements to continue. They may not be easy to see, understand, or appreciate, but semiconductor manufacturing technologies play an enormously important role in moving the tech industry and society forward.
Bob O’Donnell is the president and chief analyst of TECHnalysis Research, LLC, a market research firm that provides strategic consulting and market research services to the technology industry and professional financial community. You can follow him on Twitter @bobodtech.
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This article contains forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Forward-looking statements include any statements that are not statements of historical fact, including statements regarding industry demand trends and expectations, future technological requirements, the performance of Lam products, and Lam’s research and development efforts and priorities. Forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially from the expectations expressed, including the risks and uncertainties described in Lam’s filings with the U.S. Securities and Exchange Commission, including specifically the Risk Factors described in Lam’s annual report on Form 10-K and quarterly reports on Form 10-Q. You should not place undue reliance on forward-looking statements. This article was authored by a third party and Lam is not responsible for the statements made herein. Lam undertakes no obligation to update any forward-looking statements.