A case study on designing dummy patterning to achieve optimal etch results
- Virtual twins and process modeling can significantly reduce lengthy build-and-test cycles
- Engineers can catch flaws such as etch loading effects that impact uniformity and yield
Standard electronic design automation (EDA) tools can be used to produce a semiconductor layout, which can be used to manufacture a device with targeted performance specifications. Unfortunately, designers have learned from experience that process capabilities on semiconductor manufacturing equipment can limit device yield and performance of any idealized device layout.
Even though every polygon in the layout might abide by previously defined design rules, new process and equipment capabilities create additional challenges during design and development. Normally, designers obtain feedback from process engineers during the design cycle and adjust their original layout to compensate for actual wafer test results.
Product release cycles in semiconductor development are strongly impacted by the number of feedback and learning cycles (the learning curve)—to say nothing of increased costs. Fabricating different layouts on wafer can take months, leading to substantial product delays. Engineers need a better way to reduce these “build and test” learning cycles to accelerate time-to-market.
One of the best ways to compress semiconductor development time is to build virtual or digital twins of a proposed semiconductor device using known device physics and accumulated device data.
- Every wafer manufacturing process provides valuable data, which can be used to build a virtual twin and predict future process behavior.
- Prior wafer data can be used to calibrate a physics-based process model, which can then be used to develop an optimal design and manufacturing strategy.
In this study, we use a simple example and proven three-step methodology to optimize semiconductor design using process modeling.
1. Define the problem
In our example, a process engineer develops a process recipe for a memory device containing slit etches. Upon building the device on wafer, the engineer learns that the slit etch structures have a uniformity issue at the bottom of structure (see Figure 1).
This uniformity problem is caused by etch loading effects, where the density of device patterns can impact on-wafer etch rates and generate non-uniform etch results. This effect is well-known to the engineer, so the engineer tells the layout designer to modify the layout by adding dummy patterns. The engineer knows that dummy patterns could ameliorate etch loading problems. Unfortunately, both the engineer and layout designer don’t know the exact type of dummy layout patterns that would generate a uniform flat surface at the bottom of the slits.
Figure 1: Top view of etch result simulation (left), cross-section of etch result (middle), bottom profile extracted from simulation model (right).
2. Develop an etch process model to quantify process behavior
The engineer decides to make a virtual twin (process model) of the etch process to mimic the actual behavior of the wafer process and to quantify the impact of etch loading effects. The engineer’s goal is to discover the relationship between the density of newly added dummy patterns and the etch depth (and uniformity) of slit patterns.
Figure 2: (Left) Etch simulation model for dummy patterns. (Right): The etch simulation displays two different regimes (up and down arrows) when comparing etch depth versus opening width.
The existing etch process model (Figure 2) contains two different mechanisms of action and exhibits different behavior for small openings versus large openings of dummy patterns. This makes it difficult to determine a layout pattern that optimizes the bottom etch profile.
3. Perform statistical analysis to identify critical parameters
The “as-designed” layout was generated with a targeted 10 nm slit width. The process engineer decides to improve etch bottom uniformity by adding dummy patterns between the slits using a process model (Figure 3). Theoretically, the dummy patterns should produce larger openings and slow down the etch process.
Figure 3 (Left): Original layout. (Right): Modified layout that has additional dummy patterns (in green) to produce larger openings during the etch process.
To determine the relationship between the dummy pattern width and etch uniformity, the engineer establishes nine measurement points in the process model to quantify the standard deviation of the material thickness remaining after the etch process (Figure 4).
Figure 4: Measurement points used to quantify etch uniformity, which is defined by the remaining films standard deviation of the thickness.
The engineer then runs a DOE (design of experiments) and uses a statistical analysis to determine the most critical parameter impacting etch depth and uniformity. The engineer discovers that the dummy pattern’s Y bias is the most critical parameter (Figure 5).
Figure 5: Statistical analysis results showing that the most critical parameter is the Y bias of the dummy pattern.
Further statistical analysis is then used to find the optimum Y bias of the dummy patterns to optimize etch uniformity. Using a model of their current etch process, the engineer finds the optimal Y bias of the dummy patterns that minimize the standard deviation of the etch depth at nine measurement points (Figure 6).
Figure 6 (Left): Optimal Y bias of dummy pattern based on statistical analysis. (Right): Etch simulation result using optimum Y bias.
Conclusion
As semiconductor technology and manufacturing become more complex, real-world process capabilities will cause what are considered “ideal” designs to deviate from actual manufacturing results, as seen in this example.
Layout designers and process engineers need to collaborate, identify manufacturing process limitations, and understand the impact of process limitations on idealized layouts. If they do not, silicon wafers, expensive fab equipment, and (most importantly) time will be wasted on wafer-based testing.
By using physics-based process models and a database of known process results, virtual twins for each process can be created to more quickly identify optimal process solutions. Process models and limited silicon-based data can then be used to create semiconductor manufacturing virtual twins, reduce “build and test” cycles and accelerate time-to-market.
James Kim is a senior semiconductor process and integration engineer, Semiverse® Solutions.