- Advanced packaging makes it possible to manufacture higher performing, next-gen chips
- Packaging integrates multiple chips into a single package to improve performance and cost
Packaging is how semiconductor chips are connected to each other, increasingly to enable high performance in a small footprint. Advanced packaging describes the many novel ways chips are built and connected to fit on smaller footprint, be higher performing, and use less energy.
- Why it matters: Advanced packaging is necessary for smaller, more efficient, and better performing logic and memory chips used for artificial intelligence (AI), which requires more powerful computational capabilities and faster processing of large datasets.
Advanced packaging extends Moore’s Law by enabling more transistors on higher performing, smaller chips.
- Driving the news: The growth of advanced packaging is projected to reach a market size of $119.4 billion by 2032.
Advanced Packaging in High Bandwidth Memory
High bandwidth memory (HBM) is a prime example of advanced packaging in use today. HBM is an advanced computer memory design that plays a key role in AI by storing enormous datasets close to a graphic processing unit (GPU) for quick access.
HBM incorporates several advanced packaging techniques:
- 2.5D and 3D architecture. These configurations significantly reduce the distance that data must travel, improving communication speed and energy efficiency.
- In 2.5D packaging, dynamic random-access memory (DRAM) chips are placed adjacent to each other and then onto a silicon interposer.
- In 3D integration, multiple DRAM chips are stacked vertically instead of being spread out horizontally.
- Through silicon vias (TSVs): These are vertical structures used in 2.5D and 3D packaging that connect and pass electrical signals between chips. Data can be exchanged rapidly through these high-speed channels.
- Chip on Wafer on Substrate (CoWoS): HBM is often combined with logic chips (e.g., CPUs and GPUs) onto an interposer and then on a single high-density substrate using this advanced packaging method.
In an advanced packaging technique called “Chip on Wafer on Substrate” (CoWoS), logic (GPU) and memory (HBM) chiplets sit next to each other on a wafer, which is then cut into chips and packaged on a high-density substrate
Dig deeper: A high-density substrate is the foundational layer in advanced packaging that connects silicon dies to the printed circuit board (PCB). It routes signals, provides mechanical support, and manages heat. What makes it “high-density” is its ability to support fine-pitch interconnects, multi-layer routing, and compact form factors—all essential for modern chip architectures like 2.5D, 3D, and CoWoS.
NVIDIA's H100 AI chip is an example of CoWoS, combining one powerful GPU with six HBM stacks, each of which are formed by vertically connecting eight to 12 HBM chips. The H100 chip is considered a breakthrough for AI and is specifically designed for AI applications, particularly natural language processing and large language models.
- The H100 AI chip delivers up to 30 times faster AI inference performance compared to its predecessor, according to NVIDIA.2
Lam’s Leadership in Advanced Packaging
Lam Research invests heavily in research and development (R&D) and collaborates with foundries, chip manufacturers, and consortia to develop the advanced packaging technologies that help drive the AI era.
In addition, Lam’s advanced packaging solutions are already being used by many customers today, including the following:
- Coronus® HP and DX bevel deposition and etch tools increase yield performance by selectively removing potential defects and unwanted materials from the wafer’s edge. DX also deposits material at the wafer’s edge, a groundbreaking advancement that helps with bevel protection and/or reconstruction to improve edge bonding.
- DV-Prime® strip/clean delivers operational flexibility with up to three chemistries and high productivity. Its backside thinning ensures superior uniformity and thickness consistency.
- Kallisto™ enables fine line plating <10µm on various materials including organic and glass core technologies and through glass via metallization on a glass core, processing panels as large as 1.1 m x 1.3 m.
- PHOENIX™ delivers the highest output per footprint for 515 mm x 510 mm panels, processing up to 120 panels per hour.
- SABRE® 3D electrochemical deposition provides superior bump height uniformity and co-planarity control with high plating rates and footprint efficiency. It also delivers perfect wiring inside complex features with zero defects and excellent conductor properties.
- Striker® Oxide atomic-layer deposition provides greater than 100% step coverage.
- Syndion® plasma etch provides extreme precision for structure formation with smooth, repeatable profiles at fast rates.
- VECTOR DT™ provides industry-first carrier-less backside deposition. This backside deposition allows for precise wafer shape management that improves bonding yield.
Glossary
- 2.5D packaging: Placing multiple chips adjacent to each other and then onto a silicon interposer.
- 3D packaging: Stacking wafers and/or dies vertically (three-dimensional) and connecting them electrically using through-silicon vias (TSVs).
- 3D NAND: A device architecture in which memory cells are arranged vertically (three-dimensional) rather than horizontally (planar) to increase memory bit density.
- Chip on Wafer on Substrate (CoWoS): Packaged chips are adhered to an interposer and high-density interconnect board.
- Chiplet: Functional circuit blocks, often reusable intellectual property (IP) blocks, that are manufactured and recombined on a high-density interconnect.
- Fan out wafer level packaging (FOWLP): An advanced packaging technique that creates a package in a round 300/330 mm format.
- Heterogeneous packaging: Advanced packaging of multiple different chips.
- Interposer: A high-performance layer that enables chip-to-chip communication at speeds and densities that are impossible with conventional substrates alone.
- Panel-level packaging (PLP): An emerging advanced packaging technique where chips are attached to larger format carrier substrates that could be square or rectangular. The use of large format enables more chips per area resulting in lower per unit cost.
- Substrate: A high-density interconnect board that is the starting material for the semiconductor manufacturing process, typically an organic material like fiberglass-reinforced resins. The substrate provides mechanical support, electrical insulation, and thermal dissipation.
- Substrate-level packaging: Connecting electronic components, especially integrated circuits (ICs), onto a specialized base material called an IC substrate. See also Panel-level packaging.
- Through-silicon via (TSV): A structure that creates vertical electrical connections through a die or a wafer. TSVs enable higher functionality in smaller forms.