Blog

Soumya has automated Lam’s product software testing and processes for 19 years. The software she works on allows us to validate the behavior of our tool's software at any fab remotely. Soumya...

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic...

SEMICON Korea 2023 kicked off with a keynote speech, “Accelerating Innovation – From Lab to Fab,” delivered by Pat Lord, EVP of the Customer Support Business Group and Global Operations. Pat...

Metryx marked 200th tool shipment by donating science equipment to a local high school

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic...

At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew off a robot blade...

“Engineering a Greener Fab” was the theme of the Lam Research Technical Symposium, Lam’s premiere forum for intellectual and scientific sharing.

Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions...

Lam Research was the platinum sponsor of the 27th gathering of SEMICON Taiwan, held September 14 to 16. More than 45,000 attendees examined 2,450 exhibition booths showing the latest industry...

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce...