Blog

SEMICON Korea 2023 kicked off with a keynote speech, “Accelerating Innovation – From Lab to Fab,” delivered by Pat Lord, EVP of the Customer Support Business Group and Global Operations. Pat...

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic...

Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions...

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce...