- IBM and Lam collaborate to develop processes that can scale logic chips beyond 1 nm
- Lam's Aether dry resist is key, with fewer process steps in high-NA EUV lithography
High-NA EUV promises the resolution needed to keep scaling logic chips, but it faces a core challenge: At the feature sizes High-NA EUV is designed to print, stochastic noise (statistical variation in photon absorption) can create more defects. At such a small scale, the physics becomes less forgiving as the patterns get smaller.
A new Tom’s Hardware article shares how a five-year IBM–Lam partnership aims to speed the solution by validating manufacturable high-NA EUV process flows. The process pairs Aether® dry resist with Lam etch and deposition to improve pattern fidelity, reduce steps, and accelerate the path to sub 1-nm node innovation.
The companies will work together at IBM Research's NY Creates Albany NanoTech Complex, focusing on Lam's Aether dry resist technology, Kiyo® and Akara® etch platforms, and Striker® and ALTUS® Halo deposition systems.
As noted in the article, the collaboration is a significant opportunity for Lam to establish Aether as the validated dry resist solution for high-NA EUV logic. The five-year commitment with IBM “builds process familiarity and customer confidence well before foundries are making resist process decisions for their sub-1nm nodes.”
Read the article to learn more about the IBM and Lam partnership why Aether is gaining momentum as a key enabler for high-NA EUV.
Related Articles
- Press Release: IBM and Lam Research Announce Collaboration to Advance Sub-1nm Logic Scaling
- Everything You Need to Know About Aether
- 3D Dry Resist: How Aether Technology Enables AI‑Era Memory Scaling
- Press Release: Lam Research and JSR Corporation/Inpria Corporation Enter Cross-Licensing, Collaboration Agreement to Advance Semiconductor Manufacturing