- Small variations in mandrel and spacer dimensions can impact DRAM performance and yield
- Study using Monte Carlo virtual fabrication helps define safer process windows
As DRAM and logic technologies scale to increasingly tighter pitches, the patterning requirements exceed the limits of conventional single-exposure DUV lithography. In advanced nodes such as D1b (1-beta), active-area (AA) pitches fall in the range of 22 to 26 nm, well below the capability of single patterning. To achieve these sub-lithographic dimensions, advanced multi-patterning schemes such as Self-Aligned Quadruple Patterning (SAQP) are widely employed.
- Active-area (AA) fins are narrow, parallel silicon lines that define the DRAM transistor active region.
- SAQP is a spacer-based patterning flow that multiplies lithography-defined lines into much tighter pitch features.
But SAQP’s multi-step spacer flow can amplify small variations in mandrel critical dimension (CD), deposition conformality, and etch behavior into pitch walk. When pitch walk is combined with lithography-driven line-edge roughness (LER), the process window can collapse into line-bridge defects. In other words, this SAQP process can make small mistakes bigger, causing problems like lines touching each other and electrical issues.
The Semiverse® Solutions team used Monte Carlo virtual fabrication to evaluate these complex interactions, reveal the key parameter interactions, and define a safer SAQP process window to avoid costly wafer experiments. Although this study examined DRAM, the techniques demonstrated in this article can also be applied to logic and other device technologies.
DRAM Patterning Sequencing
The full process sequence of DRAM patterning starts with lithography-defined mandrels, followed by two cycles of spacer deposition, spacer etch, and mandrel removal (Figure 1).
Figure 1. SAQP starting stack and process sequence.
Ideally, one mandrel yields four perfectly equidistant lines and trenches; in practice, any variation in mandrel width or spacer thickness is propagated through subsequent process steps, producing alternating trench widths. This non‑periodicity (i.e., pitch walk) is a primary challenge in multi‑step patterning and can misalign wordlines (WL), bitlines (BL), and contacts.
Mandrel width deviation also arises from lithography‑induced line edge roughness (LER), which is driven by stochastic photon flux (shot noise) and random acid diffusion.1 The interaction of pitch walk and LER can generate Line Bridge defects, where neighboring lines touch and create electrical shorts. Since these effects are interdependent, establishing a safe SAQP process window is critical.
Study on Pitch Walk Conducted with Virtual Fabrication
A virtual environment was established using input process parameters that directly influence pitch walk. Dielectric Anti-Reflective Coating (DARC) and Spacer1 etch isotropy are grouped as Isotropy1, while Mandrel1, Mandrel2, Hardmask1, and Spacer2 etch isotropies are grouped as Isotropy2, distinguishing relatively isotropic from more anisotropic etch processes. Lithography focus-exposure variations that impact the printed CD are represented by lithography variation, while deposition conformality controls spacer sidewall coverage on Mandrel1 and Mandrel2. The initial print CD is set to 60 nm, resulting in ideal 15-nm line and trench CDs, with a pitch walk specification limit of 7.5 nm.2
Virtual metrology steps were integrated into simulations to quantify pitch walk and line bridge. Figure 2 displays the relationship between mandrel and spacer widths and final line and trench CDs. Pitch walk is computed from trench CDs and labeled as α, β, and γ in Figure 2, and by using the equations shown below.3,4
α = Spacer1 thickness = Trench CD1 (T1)
β = Mandrel CD – 2 x Spacer2 thickness = Trench CD2 (T2)
γ = Mandrel pitch – Mandrel CD − 2 x Spacer1 thickness − 2 x Spacer2 thickness = Trench CD4 (T4)
Pitch walk = max(α, β, γ) − min(α, β, γ)
Figure 2. Critical dimension transfer in the SAQP process.
The trench numbering scheme is shown in Figure 3a. Even‑numbered trenches are most susceptible to line bridges, as pitch walk-LER interactions can merge adjacent spacer walls at these locations, forming bridges (see Figure 3b).
Figure 3a. Trenches (SAQP final features) T1-T5 are considered for trench CD measurement to achieve α, β, and γ values. Figure 3b. Line bridge defect at an elevated LER of 2 nm.
Variation Impacts
The baseline parameters and their standard deviations, referred to as the Process of Record (POR), are detailed in Table 1.
| Parameter Name | POR Nominal | POR Width/Std |
| Isotropy1 | 0.125 | 0.024 |
| Isotropy2 | 0.055 | 0.014 |
| Dep. conformality | 0.875 | 0.041 |
| Spacer1 thickness | 28 nm | 1.3 nm |
| Spacer2 thickness | 20 nm | 1.3 nm |
| LER amplitude | 1 nm | 0.33 nm |
| Lithography variation | 0 nm | 0.83 nm |
Figure 4a displays the substantial variation applied to each parameter. Patterning results were evaluated independently for each parameter, and the corresponding pitch walk reflects the influence of that single parameter alone.
However, this type of isolated assessment does not represent actual fabrication conditions. One of the key advantages of virtual fabrication is its ability to incorporate interactions among all process parameters simultaneously. For example, simultaneous deviations of multiple parameters from their POR values can sometimes collectively induce a line‑merge defect, as shown in Figure 4b, even though this defect may not appear when each parameter is evaluated in isolation. Hence, it is helpful to have a combined parameter variation study using a Monte Carlo Design of Experiments (DOE) in SEMulator3D® Analytics.
Figure 4a. Input process parameters varied separately, and their respective pitch walk values. Figure 4b. Virtual fabrication enabling the combined variation of all the input process parameters, resulting in a line-merge defect.
DOE Results
A pitch‑walk range of 0 to 7.5 nm was used as the pass/fail criteria for all trials (not including LER and fin merge failures), as shown in Figure 5a. The maximum pitch walk success rate of 83.89% was achieved during process window optimization by using a reduced standard deviation compared to the original POR standard deviation (Figure 5b).
Figure 5a. Process window with a green marker meets minimum pitch walk success criteria (0, 7.5 nm) without LER and without line merge defects. Figure 5b. Process window optimization indicates a maximum pitch walk success rate of 83.89%.
Parameter Interactions
The collective influence of combined parameter variability is further detailed in the contour plot matrix in Figure 6. The data reveals that pitch walk is not the result of any single isolated variable but emerges from complex interactions.
For instance, the combination of high Isotropy1 and specific Litho Variation (CD Bias) push the pitch walk to extreme values (> 45 nm). Conversely, lower Isotropy2 levels combined with controlled spacer thicknesses maintain the pitch within the spec limits. This matrix serves as a sensitivity map, highlighting that tightening the budget for one parameter often requires simultaneous adjustment of other parameters to prevent pitch walk degradation.
Figure 6. Contour plot matrix showing the impact of key process variable interactions on pitch walk.
Finally, Figure 7 demonstrates the physical consequences of various process variations, specifically how pitch walk magnitude interacts with LER to trigger line bridge defects.
Figure 7. Interaction of pitch walk with LER leading to a line bridge defect. In this demonstration, the LER is introduced as Gaussian noise at a cut-off frequency of 8 µm-1.
The visualization shows that at a low LER (0.5 nm) and minimal pitch walk (1.6 nm), the lines remain distinct and functional. However, as these values increase, the “process window” collapses. When pitch walk reaches 6.6 nm even with a low LER, or when the LER hits 1.5 nm even with a low pitch walk, the lines start merging. Thus, as LER amplitude increases, the tolerance for Pitch Walk shrinks.
Conclusion
Using virtual fabrication, this study successfully evaluated the interactions among process variables that influence pitch walk. The simulations demonstrate that virtual fabrication is a highly efficient method for identifying optimal process parameter combinations. By defining the process window prior to physical wafer-level experiments, virtual fabrication serves as a critical tool for accelerating process development during advanced DRAM technology development.
Roopa Hegde and Swapnil Kailash are software applications technical lead engineers with Lam Semiverse® Solutions.
References
1 C. A. Mack. 2006. “Line Edge Roughness,” Field Guide to Optical Lithography, SPIE Press, Bellingham, WA (2006), https://spie.org/publications/spie-publication-resources/optipedia-free-optics-information/fg06_p66_line_edge_roughness.
2 J. Mulkens et al. 2017. “Patterning Control Strategies for Minimum Edge Placement Error in Logic Devices,” Metrology, Inspection, and Process Control for Microlithography XXXI, SPIE, March , p. 1014505. doi: 10.1117/12.2260155.
3 S. Baudot et al. 2018. “N7 FinFET Self-Aligned Quadruple Patterning Modeling,” 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September, pp. 344–347. doi: 10.1109/SISPAD.2018.8551646.
4 B. Vincent et al. 2019. “Virtual Fabrication and Advanced Process Control Improve Yield for SAQP Process Assessment With 16 nm Half-pitch,” Advanced Etch Technology for Nanopatterning VIII, SPIE, March, pp. 119–127. doi: 10.1117/12.2518099.