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With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic...

SEMICON Korea 2023 kicked off with a keynote speech, “Accelerating Innovation – From Lab to Fab,” delivered by Pat Lord, EVP of the Customer Support Business Group and Global Operations. Pat...

Metryx marked 200th tool shipment by donating science equipment to a local high school

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic...