- Despite being fabricated on the same wafer, some dies perform differently from others
- Engineers can use virtual fabrication to understand and avoid within-wafer variations
One of the unavoidable aspects of chip manufacturing is that some dies on a wafer perform differently than others, even though they were made together on the same wafer. This blog dives into that mystery and provides a way to predict and fix these issues.
Imagine baking cookies. If your oven has hot and cold spots, some cookies will be perfect; others burnt. That’s what happens in chip manufacturing. Variations across the wafer lead to unpredictable results. Yields drop, and costs go up.
Instead of guessing why this happens, engineers can now use virtual fabrication to gain a better understanding of within-wafer variations. Think of virtual fabrication as a super-smart simulator that mimics the entire chip-making process.
We start with a digital twin of the fabrication process (Figure 1). The baseline version of the digital twin assumes perfectly uniform deposition and etch processing and perfectly straight profiles.
Figure 1. Virtual fabrication model of a (14-nm FinFET) transistor showing key manufacturing steps. The spacer deposition (6) and source/drain Epi (7) steps are the subject of this work.
Within-wafer variation data from a deposition tool can then be fed into our simulation model (the digital twin) to study different variations in output metrics, such as gate oxide contact area or device figures of merit.
Figure 2 displays variations in etch rate across different parts of the wafer, which can be fed into the simulation.
Figure 2. (a) Wafer map etch rate data. (b) Distribution of the etch rates. (c) Distribution of the etch rates by wafer regions.
We performed a 2,000 run Monte Carlo simulation, where we looked at etch results across different wafer locations by varying the polar coordinates in the model. The distance from the center of the wafer was varied from 0 to 150 mm in the simulation (see Figure 2a), and the angle from an arbitrarily chosen x-axis was varied from 0 to 360 degrees.
Figure 2 demonstrates that there’s a gradient (or difference in the etch rate) as we travel from the center of the wafer to the edge of the wafer.
The contact area between the gate oxide and the poly gate, and the contact area between high-k dielectric material (Hafnia) and the gate metal were both measured, and the differences in their values across the wafer were also investigated (Figure 3a).
Figure 3. Wafer maps of (a) the contact area between the gate oxide and poly gate, and the contact area between the high-k dielectric material (Hafnia) and the gate metal and (b) device figures of merit displaying transistor operating characteristics.
Device simulation was then performed to analyze transistor characteristics such as threshold voltage, subthreshold swing, and DIBL (drain induced barrier lowering) at different locations across the wafer (Figure 3b).
Limiting variations
A linear regression of the results suggested that constraining etch rate variations to within 7% of the mean value would deliver acceptable device performance across all dies (all device characteristics would be kept within lower and upper control levels). This was verified with a second Monte Carlo simulation (Figure 4).
Figure 4. Linear regression indicates that limiting Spacer Nitride thickness deviations to ±7% will ensure that all devices remain within specification.
Recipe changes
Next, we considered three potential process recipe changes to improve within-wafer die performance and yield. Each recipe used different distributions of etch rate variability. While the difference between the maximum and minimum etch rates were identical, the gaussian peaks were at the center, donut, and edge regions in the three cases, respectively.
The wafer simulation results indicate that the third recipe resulted in the minimum standard deviation of transistor threshold voltage across the wafer (Figure 5).
Figure 5. Comparison of impact on threshold voltage using three potential recipes. Each recipe had a different etch rate variability. Recipe 3 has the smallest standard deviation and highest yield.
This type of study can be used to predict the impact of process recipe changes on within-wafer die performance and yield. Crucially, this analysis can help understand the impact of cross-wafer variations caused by tools from different vendors and how Lam’s Semiverse® Solutions can help mitigate the impact of these variations.
Conclusion
As semiconductor devices scale down in size, process variability and within-wafer variations become a critical challenge. Virtual fabrication provides a cost-effective, data-driven way to predict within-wafer variability problems before they occur on the fab floor. By simulating thousands of scenarios, engineers can identify sensitive parameters, optimize recipes, and improve die yield across a wafer, without the time and cost of extensive wafer-based testing.
Sam Sarkar is a senior semiconductor process and integration engineer with Semiverse® Solutions at Lam Research.