Blog

Tiny changes in critical dimension, gate height, and similar features of advanced logic devices, such as FinFET SRAM, can affect yield. Through virtual experiments using the SEMulator3D® platform, the Semiverse Solutions team discusses how material stress and mechanical deformation resulting from these changes can be managed to enhance device performance.

Ion Beam Etch (IBE) is a promising technology for extreme ultraviolet (EUV) lithography by significantly improving line edge roughness (LER) and line width roughness (LWR).

DWMG structures can help improve DRAM by reducing energy waste. These structures fix a known flaw called “gate-induced drain leakage” (GIDL).

To evaluate stress and mitigate its effects, predictive 3D process models can be used to predict the impact of mechanical stress on yield and performance.

The latest advancements in semiconductor interconnect technologies, focusing on optimizing metal pitch structures for sub-2nm nodes.

Intelligent machines enable faster design, production, maintenance, and process improvements. Numerous benefits can be gained from self-aware, self-maintained, and adaptive tools.

By leveraging compact and neural network models, we predict capacitance performance with unprecedented accuracy.

Digital twins help increase precision, affordability, sustainability, and speed-to-solution. Semiverse Solutions helps find the best process flow or recipe out of infinite combinations.

On how to reduce transistor capacitance at the 5nm node using a source/drain contact recess.

Abstract As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance.