Blog

By leveraging compact and neural network models, we predict capacitance performance with unprecedented accuracy.

Digital twins help increase precision, affordability, sustainability, and speed-to-solution. Semiverse Solutions helps find the best process flow or recipe out of infinite combinations.

On how to reduce transistor capacitance at the 5nm node using a source/drain contact recess.

Abstract As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance.

As semiconductor complexity increases with scaling, specialized expertise in areas like plasma physics and artificial intelligence (AI) becomes crucial. Lam faces challenges in workforce...

Abstract In this article, we demonstrate a pathfinding technique for a novel Vertical DRAM technology. First, we identify important process parameters (defined by current semiconductor production...

Li Fei Sun won for her paper on smart tools and ML solutions in semiconductor manufacturing In the past four years, Lam engineers have won the top award three times At Lam Research, we take pride...

There are still many challenges to be overcome before CFET designs become mainstream, but this new 3D architecture represents a promising new direction for the future of computing.

On the use and benefits of virtual fabrication in the development of DRAM saddle fin profiles

We explore the causes and implications of asymmetric wafer defects in semiconductor manufacturing. We also consider the use of virtual process modeling to understand and mitigate these structural failures.