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|May 7, 2026|As semiconductor manufacturing grows more complex, sensor‑driven intelligence is emerging as a critical enabler of autonomous, data‑driven fabs.
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|Apr 27, 2026|Lam Research won two prestigious 2026 Edison Awards, for ALTUS® Halo and Akara®
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|Apr 27, 2026|Pattern-dependent etch can lead to variations across the same chip. Dummy fill and SEMulator3D® help reduce shallow trench isolation and recess nonuniformity.
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|Apr 14, 2026|Everything—NAND, Logic, DRAM, and packaging—is going 3D. The 3D era demands deeper etch and precise deposition to build taller, tighter devices.
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|Apr 8, 2026|In this edition of Semi 101, we explore the evolution of transistor architectures that have enabled logic scaling.
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|Mar 31, 2026|In DRAM SAQP, small process variations can compound into pitch walk and, with LER, create line-bridge defects. Monte Carlo virtual fabrication reveals these interactions to tighten process windows and reduce wafer experimentation.
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|Mar 24, 2026|AI is compressing chip development timelines and raising the stakes for equipment suppliers Here is how Lam is responding Speed has always mattered in the semiconductor industry. What is different...
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|Mar 17, 2026|IBM and Lam Research have partnered in a five-year collaboration to develop processes that enable logic chip scaling beyond the 1nm node using high-NA EUV lithography.
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|Mar 10, 2026|The 2026 Lam Capital Venture Competition is a unique event that connects semiconductor startups with industry leaders, investors, and technical experts to advance AI-enabled semiconductor technologies.
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|Feb 26, 2026|SEMulator3D® Analytics is useful in calibrating FinFET device profiles, helping engineers achieve high precision in modeling fin etch depth and critical dimensions.
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|Feb 24, 2026|With AI's overwhelming demand for DRAM, Lam is accelerating its response with streamlined workflows and specialized tools help speed efficiency, yield, and cost savings.
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|Feb 17, 2026|Boise investment keeps Lam’s capabilities tightly coupled to customer roadmaps
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|Feb 13, 2026|DRAM scaling has reached the angstrom level—and the advanced architectures and processes that make higher performance and lower cost per bit possible. Watch now to see how memory keeps getting smaller.
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|Feb 12, 2026|Lam Research and CEA-Leti have formed a multi-year partnership to accelerate the development of specialty technology devices critical for AI hardware. This collaboration focuses on advancing materials, processes, and manufacturable solutions to improve energy efficiency and performance in AI data centers.
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|Feb 5, 2026|With over 40 years in making semiconductor equipment, Lam Research has demonstrated leadership in etch and deposition that meet the precision and yield demands of advanced packaging, helping customers ramp new technologies with confidence.
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|Jan 29, 2026|Not every chip on a wafer behaves the same; even small variations can impact yield. The Lam Semiverse Solutions team explains how engineers use virtual fabrication to understand why these differences happen and how to fix them.
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|Jan 23, 2026|Lam’s Aether® dry‑resist technology plays a key role in enabling next-gen logic chips, including the latest 2 nm node
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|Jan 12, 2026|DRAM is volatile memory that has the advantages of simplicity and high density. Lam is continuously innovating for each DRAM inflection as data-intensive AI requires more and more data at higher speeds.
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|Dec 18, 2025|Manufacturing breakthroughs in advanced chip packaging—especially heterogeneous integration and 3D stacking—are critical to powering the future of AI.
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|Dec 9, 2025|Watch the video on the next wave of semiconductor innovation with advanced packaging solutions from Lam Research.
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|Nov 19, 2025|Self-aligned backside contact (SABC) architectures in advanced GAA transistors expand the process window, reducing defects and improving chip yield.
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|Nov 5, 2025|Molybdenum hybrid metallization is driving innovation in semiconductor materials for AI, 5G, and data centers. These advances boost performance, sustainability, and efficiency in chip manufacturing.
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|Oct 31, 2025|The article discusses the challenges and solutions for back-end-of-line (BEOL) patterning at the 3-nm semiconductor node, focusing on controlling critical process parameters to manage edge placement error (EPE) and critical dimension (CD) variability.
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|Oct 29, 2025|Students at a growing number of U.S. schools learn the “why” of advanced 3D processes SEMulator3D® helps students with immersive training on leading edge technologies.
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|Oct 23, 2025|At Lam we're pairing human ingenuity with advanced mechatronics and automation to solve big challenges for our customers. That same spirit will be on display at the 2025 FIRST Global Challenge.
