Blog

Lam’s Semiverse Solutions team used digital twin modeling to explore a self-aligned CFET architecture that could help extend CMOS scaling beyond 10 Å.

AI is increasing demand for larger and more complex chip packages. Traditional wafer-based packaging faces scaling challenges for large-format designs. Panel-level processing may improve...

Lam Research broke ground on a new advanced R&D lab in Tualatin, Oregon, expanding cleanroom capacity and strengthening its global lab network.

Lam Semiverse® Solutions engineers used SEMulator3D® stress modeling to show how channel thickness, fin width, and lateral etch can be optimized to reduce stress non-uniformity and improve gate-all-around nanosheet transistor performance.

Lam's labs are part of a purpose-built, globally integrated R&D infrastructure designed to accelerate innovation across technology inflections.

Learn how feedforward control helps semiconductor manufacturers reduce wafer scrap and improve yield. Semiverse Solutions simulation demonstrated a pass-rate increase from 60.82% to 96.77% through intelligent process correction.

SABRE 3D is an electrochemical deposition solution engineered for precision copper plating (the critical wiring of modern semiconductor devices).

A joint paper from Lam Research, ASML, and imec puts 20 nm metal pitch in focus

AI is redefining semiconductor scaling Audrey Charles discusses the technologies, partnerships, and innovations that will define the future of semiconductor scaling AI is driving unprecedented...

SEMulator3D virtual fabrication optimizes backside power networks by modeling nTSV-to-BPR connectivity.

Panel-level packaging enables higher area efficiency and scalability for large-format advanced packages

See how Lam’s dry resist technology helps enable the precision, flexibility, and efficiency needed for next-generation EUV chipmaking.

Digital twin technology combined with machine learning enables a dramatic yield improvement from 1.6% to 87.2% in GAA logic manufacturing by simulating and optimizing the entire fabrication process.

The 2026 Lam Capital Venture Competition highlighted breakthrough semiconductor innovations with Lightfinder winning for its chip-scale optical sensing technology designed to enable real-time, in-tool metrology. This event showcased Lam Research's leadership in supporting startups that build the AI backbone for semiconductor manufacturing.

Equipment Intelligence® encompasses Lam’s technology portfolio both on and off tool to leverage sensors, data, algorithms, artificial intelligence, and robotics automation to make tools more autonomous and productive.

As semiconductor manufacturing grows more complex, sensor‑driven intelligence is emerging as a critical enabler of autonomous, data‑driven fabs.

Lam Research won two prestigious 2026 Edison Awards, for ALTUS® Halo and Akara®

Pattern-dependent etch can lead to variations across the same chip. Dummy fill and SEMulator3D® help reduce shallow trench isolation and recess nonuniformity.

In semiconductor manufacturing, precision is everything. As chips become more advanced and fabs operate under unprecedented pressure to meet AI-driven demand, even the smallest maintenance error...

Everything—NAND, Logic, DRAM, and packaging—is going 3D. The 3D era demands deeper etch and precise deposition to build taller, tighter devices.

In this edition of Semi 101, we explore the evolution of transistor architectures that have enabled logic scaling.

Lam’s leadership in 3D NAND built the playbook for memory’s complex architectural transition. Companies that learn from and apply their experience will lead the way to 3D DRAM.

In DRAM SAQP, small process variations can compound into pitch walk and, with LER, create line-bridge defects. Monte Carlo virtual fabrication reveals these interactions to tighten process windows and reduce wafer experimentation.

AI is compressing chip development timelines and raising the stakes for equipment suppliers Here is how Lam is responding Speed has always mattered in the semiconductor industry. What is different...

IBM and Lam Research have partnered in a five-year collaboration to develop processes that enable logic chip scaling beyond the 1nm node using high-NA EUV lithography.