Blog

Higher memory densities can be achieved with 3D NAND by increasing the number of metal and oxide layers. We looked at how to avoid tier bending and collapse that can accompany increasing layers using SEMulator3D.

Lam continues to demonstrate our commitment to both performance and sustainability

Advanced patterning techniques are essential for manufacturing next-generation semiconductor chips with extremely small and precise features, enabling higher performance, greater functionality, and improved cost efficiency in logic, DRAM, and NAND devices.

SEMulator3D® software is useful for semiconductor process modeling and virtual design Engineers can easily and vividly visualize complicated 3D structures with the tool Semiverse® Solutions,...

Gowri explains the challenges faced by chipmakers as they turn to 3D structures for logic, memory, and storage to continue Moore’s Law.

Dextro™ revolutionizes fab maintenance with sub-micron precision and AI-driven capabilities

First graduating class completes immersive, hands-on microscopy training

Driving the news: For the tenth consecutive year, Lam Research is recognized on the Fortune 500, ranking at #295. Lam first debuted on the Fortune 500 at #491 in 2016 and has grown revenue 183%...

Tiny changes in critical dimension, gate height, and similar features of advanced logic devices, such as FinFET SRAM, can affect yield. Through virtual experiments using the SEMulator3D® platform, the Semiverse Solutions team discusses how material stress and mechanical deformation resulting from these changes can be managed to enhance device performance.

Discover how Lam Research's ALTUS® Halo tool is transforming semiconductor manufacturing with molybdenum.