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Light-based interconnects dramatically improve AI computing speed, energy efficiency. Lam’s precision etch and dep tech make photonics manufacturable at scale.

SEMulator3D® Analytics is useful in calibrating FinFET device profiles, helping engineers achieve high precision in modeling fin etch depth and critical dimensions.

With AI's overwhelming demand for DRAM, Lam is accelerating its response with streamlined workflows and specialized tools help speed efficiency, yield, and cost savings.

As a viable alternative to silicon, gallium nitride (GaN) can help data centers meet the growing demands of AI by enabling more efficient power delivery and reducing energy consumption.

Boise investment keeps Lam’s capabilities tightly coupled to customer roadmaps

DRAM scaling has reached the angstrom level—and the advanced architectures and processes that make higher performance and lower cost per bit possible. Watch now to see how memory keeps getting smaller.

Lam Research and CEA-Leti have formed a multi-year partnership to accelerate the development of specialty technology devices critical for AI hardware. This collaboration focuses on advancing materials, processes, and manufacturable solutions to improve energy efficiency and performance in AI data centers.

Lam Research’s Aether dry resist technology eliminates pattern collapse and reduces defects, enabling precise, high‑aspect‑ratio features for next‑generation 3D DRAM and HBM.

With over 40 years in making semiconductor equipment, Lam Research has demonstrated leadership in etch and deposition that meet the precision and yield demands of advanced packaging, helping customers ramp new technologies with confidence.

Not every chip on a wafer behaves the same; even small variations can impact yield. The Lam Semiverse Solutions team explains how engineers use virtual fabrication to understand why these differences happen and how to fix them.

Lam’s Aether® dry‑resist technology plays a key role in enabling next-gen logic chips, including the latest 2 nm node

Fortune has named Lam to its World’s Most Admired Companies list for 2026.

Lam Research is setting the agenda for the wafer fabrication equipment industry's approach to a silicon photonics revolution

DRAM is volatile memory that has the advantages of simplicity and high density. Lam is continuously innovating for each DRAM inflection as data-intensive AI requires more and more data at higher speeds.

Lam Research improved its CDP Climate Change score from B to A-, reflecting progress toward our net zero goal and commitment to transparency.

Lam’s newest innovation, the VECTOR® TEOS 3D tool, is crafted at its Tualatin, Oregon facility by a talented local workforce known for its multidisciplinary expertise. The company’s strong commitment to employee safety, career satisfaction, and professional growth has resulted in an outstanding retention rate, making Tualatin a standout example of manufacturing excellence.

Manufacturing breakthroughs in advanced chip packaging—especially heterogeneous integration and 3D stacking—are critical to powering the future of AI.

Watch the video on the next wave of semiconductor innovation with advanced packaging solutions from Lam Research.

Micron awarded Lam for exceptional performance in front-end equipment supply.

Lam Research’s latest milestone in its global expansion is in Tualatin, Oregon. The development signals what’s next for Oregon, the Silicon Forest, and the future of American leadership in the semiconductor industry.

Self-aligned backside contact (SABC) architectures in advanced GAA transistors expand the process window, reducing defects and improving chip yield.

Startup backed by Lam Capital reduces metal contaminated liquid waste by up to 90%

Molybdenum hybrid metallization is driving innovation in semiconductor materials for AI, 5G, and data centers. These advances boost performance, sustainability, and efficiency in chip manufacturing.

As a founding donor of the Semiconductor Pathways Fund, Lam Research is taking action to ensure promising STEM students can complete their degrees and power the next generation...

The article discusses the challenges and solutions for back-end-of-line (BEOL) patterning at the 3-nm semiconductor node, focusing on controlling critical process parameters to manage edge placement error (EPE) and critical dimension (CD) variability.