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By leveraging compact and neural network models, we predict capacitance performance with unprecedented accuracy.

Digital twins help increase precision, affordability, sustainability, and speed-to-solution. Semiverse Solutions helps find the best process flow or recipe out of infinite combinations.

On how to reduce transistor capacitance at the 5nm node using a source/drain contact recess.

Abstract As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance.

As semiconductor complexity increases with scaling, specialized expertise in areas like plasma physics and artificial intelligence (AI) becomes crucial. Lam faces challenges in workforce...

Abstract In this article, we demonstrate a pathfinding technique for a novel Vertical DRAM technology. First, we identify important process parameters (defined by current semiconductor production...

Li Fei Sun won for her paper on smart tools and ML solutions in semiconductor manufacturing In the past four years, Lam engineers have won the top award three times At Lam Research, we take pride...

There are still many challenges to be overcome before CFET designs become mainstream, but this new 3D architecture represents a promising new direction for the future of computing.

On the use and benefits of virtual fabrication in the development of DRAM saddle fin profiles

We explore the causes and implications of asymmetric wafer defects in semiconductor manufacturing. We also consider the use of virtual process modeling to understand and mitigate these structural failures.

The potential of Resistive Random Access Memory (ReRAM) as an alternative to SRAM for on-chip memory in advanced CPU applications.

Virtual process development tools can accelerate the identification of process hotspots. These techniques lead to cost savings and improved yields in chip manufacturing.

Virtual fabrication is a powerful tool to perform sensitivity analysis and provide guidance for inline process spec control

BEOL module processing faces challenges as chipmakers move to the 3 nm node and beyond. A semi-damascene integration scheme with airgap structures may help reduce RC delay time.

Lam Research and the Centre for Nano Science and Engineering (CeNSE) at the Indian Institute of Science (IISc) partner to train up to 60,000 semiconductor engineers.

DRAM is following NAND in going 3D, but architecture needs are unique and challenging. 3D DRAM is needed to keep up with the demands of graphics cards, portable devices, and more. Here's an idea of how to architect it.

Up to 60,000 engineers in India to be trained on Lam’s unique virtual fabrication platform

New portfolio joins physical and virtual semiconductor worlds into a single ecosystem

As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar...

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have...

Introduction In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic...

Introduction Cu’s resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales. The formation of...

With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic...

SEMICON Korea 2023 kicked off with a keynote speech, “Accelerating Innovation – From Lab to Fab,” delivered by Pat Lord, EVP of the Customer Support Business Group and Global Operations. Pat...

Line edge roughness (LER) can occur during the exposure step in lithography [1-2]. Similarly, etch and deposition process steps can leave a roughness on semiconductor surfaces. LER is a stochastic...

Introduction The semiconductor industry has been focused on scaling and developing advanced technologies using advanced etch tools and techniques. With decreasing semiconductor device dimensions...

Reducing the parasitic capacitance between the gate metal and the source/drain contact of a transistor can decrease device switching delays. One way to reduce parasitic capacitance is to reduce...

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of...

Introduction BEOL metal line RC delay has become a dominant factor that limits chip performance at advanced nodes [1]. Smaller metal line pitches require a narrower line CD and line-to-line...

Modern semiconductor processes are extremely complicated and involve thousands of interacting individual process steps. During the development of these process steps, roadblocks and barriers are...

Introduction As we approach the 1.5nm node and beyond, new BEOL device integration challenges will be presented. These challenges include the need for smaller metal pitches, along with support for...

Design of Experiments (DOE) is a powerful concept in semiconductor engineering research and development. DOEs are sets of experiments used to explore the sensitivity of experimental variables and...

When I was a small child, I remember watching a 1966 American sci-fi adventure movie called “Fantastic Voyage” (the Korean title was “Micro Squad”) on an old black-and-white TV. The...

SEMICON China will connect technologists to the world’s fastest growing and most dynamic microelectronics market. Held at the Shanghai New International Exhibition Centre (SNIEC) on March 17-19,...

Semiconductor process development is no easy task, with each generation of devices more difficult and expensive to create. Traditional cycles of build-and-test development are becoming obsolete,...

The SPIE Advanced Lithography symposium brings together leaders across the semiconductor industry to discuss the latest challenges in lithography and patterning. Held at the San Jose Convention...