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Lam’s Semiverse Solutions team used digital twin modeling to explore a self-aligned CFET architecture that could help extend CMOS scaling beyond 10 Å.

Lam Research’s new Silicon Valley warehouse speeds semiconductor parts retrieval and strengthens U.S. supply chain resilience.

AI is increasing demand for larger and more complex chip packages. Traditional wafer-based packaging faces scaling challenges for large-format designs. Panel-level processing may improve...

Lam Research broke ground on a new advanced R&D lab in Tualatin, Oregon, expanding cleanroom capacity and strengthening its global lab network.

Lam Semiverse® Solutions engineers used SEMulator3D® stress modeling to show how channel thickness, fin width, and lateral etch can be optimized to reduce stress non-uniformity and improve gate-all-around nanosheet transistor performance.

Lam's labs are part of a purpose-built, globally integrated R&D infrastructure designed to accelerate innovation across technology inflections.

Learn how feedforward control helps semiconductor manufacturers reduce wafer scrap and improve yield. Semiverse Solutions simulation demonstrated a pass-rate increase from 60.82% to 96.77% through intelligent process correction.

AI is redefining semiconductor scaling Audrey Charles discusses the technologies, partnerships, and innovations that will define the future of semiconductor scaling AI is driving unprecedented...

A Lam scanning electron microscope technician shares how he started a career at Lam Research and continues his journey today as a lab supervisor.

SEMulator3D virtual fabrication optimizes backside power networks by modeling nTSV-to-BPR connectivity.

Panel-level packaging enables higher area efficiency and scalability for large-format advanced packages

See how Lam’s dry resist technology helps enable the precision, flexibility, and efficiency needed for next-generation EUV chipmaking.

As AI accelerates demand for advanced chips, sustainability is becoming essential for long-term growth

Digital twin technology combined with machine learning enables a dramatic yield improvement from 1.6% to 87.2% in GAA logic manufacturing by simulating and optimizing the entire fabrication process.

The 2026 Lam Capital Venture Competition highlighted breakthrough semiconductor innovations with Lightfinder winning for its chip-scale optical sensing technology designed to enable real-time, in-tool metrology. This event showcased Lam Research's leadership in supporting startups that build the AI backbone for semiconductor manufacturing.

Equipment Intelligence® encompasses Lam’s technology portfolio both on and off tool to leverage sensors, data, algorithms, artificial intelligence, and robotics automation to make tools more autonomous and productive.

As semiconductor manufacturing grows more complex, sensor‑driven intelligence is emerging as a critical enabler of autonomous, data‑driven fabs.

Lam Research won two prestigious 2026 Edison Awards, for ALTUS® Halo and Akara®

Pattern-dependent etch can lead to variations across the same chip. Dummy fill and SEMulator3D® help reduce shallow trench isolation and recess nonuniformity.

Everything—NAND, Logic, DRAM, and packaging—is going 3D. The 3D era demands deeper etch and precise deposition to build taller, tighter devices.

In this edition of Semi 101, we explore the evolution of transistor architectures that have enabled logic scaling.

In DRAM SAQP, small process variations can compound into pitch walk and, with LER, create line-bridge defects. Monte Carlo virtual fabrication reveals these interactions to tighten process windows and reduce wafer experimentation.

AI is compressing chip development timelines and raising the stakes for equipment suppliers Here is how Lam is responding Speed has always mattered in the semiconductor industry. What is different...

IBM and Lam Research have partnered in a five-year collaboration to develop processes that enable logic chip scaling beyond the 1nm node using high-NA EUV lithography.

The 2026 Lam Capital Venture Competition is a unique event that connects semiconductor startups with industry leaders, investors, and technical experts to advance AI-enabled semiconductor technologies.

SEMulator3D® Analytics is useful in calibrating FinFET device profiles, helping engineers achieve high precision in modeling fin etch depth and critical dimensions.

With AI's overwhelming demand for DRAM, Lam is accelerating its response with streamlined workflows and specialized tools help speed efficiency, yield, and cost savings.

Boise investment keeps Lam’s capabilities tightly coupled to customer roadmaps

DRAM scaling has reached the angstrom level—and the advanced architectures and processes that make higher performance and lower cost per bit possible. Watch now to see how memory keeps getting smaller.

Lam Research and CEA-Leti have formed a multi-year partnership to accelerate the development of specialty technology devices critical for AI hardware. This collaboration focuses on advancing materials, processes, and manufacturable solutions to improve energy efficiency and performance in AI data centers.

With over 40 years in making semiconductor equipment, Lam Research has demonstrated leadership in etch and deposition that meet the precision and yield demands of advanced packaging, helping customers ramp new technologies with confidence.

Not every chip on a wafer behaves the same; even small variations can impact yield. The Lam Semiverse Solutions team explains how engineers use virtual fabrication to understand why these differences happen and how to fix them.

Lam’s Aether® dry‑resist technology plays a key role in enabling next-gen logic chips, including the latest 2 nm node

DRAM is volatile memory that has the advantages of simplicity and high density. Lam is continuously innovating for each DRAM inflection as data-intensive AI requires more and more data at higher speeds.

Manufacturing breakthroughs in advanced chip packaging—especially heterogeneous integration and 3D stacking—are critical to powering the future of AI.

Watch the video on the next wave of semiconductor innovation with advanced packaging solutions from Lam Research.

Self-aligned backside contact (SABC) architectures in advanced GAA transistors expand the process window, reducing defects and improving chip yield.

Molybdenum hybrid metallization is driving innovation in semiconductor materials for AI, 5G, and data centers. These advances boost performance, sustainability, and efficiency in chip manufacturing.

The article discusses the challenges and solutions for back-end-of-line (BEOL) patterning at the 3-nm semiconductor node, focusing on controlling critical process parameters to manage edge placement error (EPE) and critical dimension (CD) variability.

Students at a growing number of U.S. schools learn the “why” of advanced 3D processes SEMulator3D® helps students with immersive training on leading edge technologies.

At Lam we're pairing human ingenuity with advanced mechatronics and automation to solve big challenges for our customers. That same spirit will be on display at the 2025 FIRST Global Challenge.

Lam CVP David Fried explains how Fabtex Yield Optimizer is the newest Semiverse Solutions technology to help the semiconductor industry achieve higher yields

The Colorado School of Mines award is given to its most generous contributors Research investigates ways to improve etch selectivity, thermal ALD, and more Share this news with your network

Lam Research earned the 2025 SEMI Award for North America for our pioneering cryogenic etch technology

Fabtex™ Yield Optimizer is a new Semiverse® Solutions product designed to improve yield and reduce process variability in high-volume semiconductor manufacturing.

Virtual twins and process modeling speed up semiconductor development by simulating and optimizing designs before fabrication. This case study shows how to address etch uniformity issues from etch loading in slit patterns, enabling faster, more precise process optimization.

Lam Research offers a range of advanced tools and technologies designed to support semiconductor manufacturing, focusing on precision, innovation, and improving chip production processes. These solutions include etch and deposition systems, process control tools, and software products aimed at next-generation device fabrication.

Advanced packaging is a critical technology driving the performance, efficiency, and form factor improvements of AI chips, enabling the ongoing AI revolution.

HBM's 3D stacked architecture delivers 16x higher bandwidth than traditional memory. Lam Research leads the industry in HBM manufacturing equipment

TEOS 3D delivers high-quality, void-free thick dielectric film deposition for advanced packaging. Its proprietary clamping technology handles challenging high-bow wafers.